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Simple PCIe FMC carrier SPEC
Commit 7051bce9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: re-define and clean-up golden to also include DDR3. 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 13368245
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Showing with 170 additions and 127 deletions
hdl/syn/golden/.gitignore 0 → 100644
View file @ 7051bce9
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden/Manifest.py
View file @ 7051bce9
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t" syn_device = "xc6slx45t"
syn_grade = "-3" syn_grade = "-3"
syn_package = "fgg484" syn_package = "fgg484"
syn_project = "spec_golden.xise" syn_project = "spec_golden-45T.xise"
syn_tool = "ise" syn_tool = "ise"
syn_top = "spec_golden" syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi'] spec_base_ucf = ['onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ] ctrls = ["bank3_32b_32b" ]
files = [
"buildinfo_pkg.vhd",
]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden", "../../syn/common" "../../top/golden",
], "../../syn/common",
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
], ],
} }
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch # Do not fail during hdlmake fetch
try: try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read()) exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/top/golden/Manifest.py
View file @ 7051bce9
files = ["spec_golden.vhd"] # Allow the user to override fetchto using:
modules = {'local': ["../../rtl"]} # hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"spec_golden.vhd",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/golden/spec_golden.vhd
View file @ 7051bce9
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
-- description: SPEC golden design, without WR. -- description: SPEC golden design, without WR.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright CERN 2019 -- Copyright CERN 2019-2020
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware -- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except -- License, Version 2.0 (the "License"); you may not use this file except
...@@ -24,54 +24,46 @@ ...@@ -24,54 +24,46 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
entity spec_golden is entity spec_golden is
generic (
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := FALSE
);
port ( port (
-- Global ports -- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic; clk_125m_pllref_n_i : in std_logic;
gn_RST_N_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N) -- GN4124
gn_rst_n_i : in std_logic;
-- General Purpose Interface gn_p2l_clk_n_i : in std_logic;
gn_GPIO_b : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8 gn_p2l_clk_p_i : in std_logic;
-- GPIO[1] -> GN4124 GPIO9 gn_p2l_rdy_o : out std_logic;
-- PCIe to Local [Inbound Data] - RX gn_p2l_dframe_i : in std_logic;
gn_P2L_RDY_o : out std_logic; -- Rx Buffer Full Flag gn_p2l_valid_i : in std_logic;
gn_P2L_CLK_n_i : in std_logic; -- Receiver Source Synchronous Clock- gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_P2L_CLK_p_i : in std_logic; -- Receiver Source Synchronous Clock+ gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_P2L_DATA_i : in std_logic_vector(15 downto 0); -- Parallel receive data gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_P2L_DFRAME_i : in std_logic; -- Receive Frame gn_rx_error_o : out std_logic;
gn_P2L_VALID_i : in std_logic; -- Receive Data Valid gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
-- Inbound Buffer Request/Status gn_l2p_dframe_o : out std_logic;
gn_P_WR_REQ_i : in std_logic_vector(1 downto 0); -- PCIe Write Request gn_l2p_valid_o : out std_logic;
gn_P_WR_RDY_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready gn_l2p_edb_o : out std_logic;
gn_RX_ERROR_o : out std_logic; -- Receive Error gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
-- Local to Parallel [Outbound Data] - TX gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_L2P_DATA_o : out std_logic_vector(15 downto 0); -- Parallel transmit data gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_L2P_DFRAME_o : out std_logic; -- Transmit Data Frame gn_tx_error_i : in std_logic;
gn_L2P_VALID_o : out std_logic; -- Transmit Data Valid gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_L2P_CLK_n_o : out std_logic; -- Transmitter Source Synchronous Clock- gn_gpio_b : inout std_logic_vector(1 downto 0);
gn_L2P_CLK_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB_o : out std_logic; -- Packet termination and discard -- PCB version and reset button
-- Outbound Buffer Status
gn_L2P_RDY_i : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR_i : in std_logic; -- Transmit Error
gn_VC_RDY_i : in std_logic_vector(1 downto 0); -- Channel ready
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0); pcbrev_i : in std_logic_vector(3 downto 0);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_n_i : in std_logic; button1_n_i : in std_logic;
-- I2C to the FMC -- I2C to the FMC
...@@ -79,32 +71,53 @@ entity spec_golden is ...@@ -79,32 +71,53 @@ entity spec_golden is
fmc0_sda_b : inout std_logic; fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up) -- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic; fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
-- Onewire
onewire_b : inout std_logic; onewire_b : inout std_logic;
-- SPI
spi_sclk_o : out std_logic; spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic; spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic; spi_mosi_o : out std_logic;
spi_miso_i : in std_logic spi_miso_i : in std_logic
); );
end spec_golden; end spec_golden;
architecture rtl of spec_golden is architecture arch of spec_golden is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin begin
inst_spec_base: entity work.spec_base_wr
inst_spec_base : entity work.spec_base_wr
generic map ( generic map (
g_WITH_VIC => True, g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => True, g_WITH_ONEWIRE => TRUE,
g_WITH_SPI => True, g_WITH_SPI => TRUE,
g_WITH_DDR => False, g_WITH_DDR => TRUE,
g_WITH_WR => False, g_DDR_DATA_SIZE => 32,
g_simulation => False g_WITH_WR => FALSE,
g_SIMULATION => g_SIMULATION
) )
port map ( port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
...@@ -140,16 +153,25 @@ begin ...@@ -140,16 +153,25 @@ begin
spi_mosi_o => spi_mosi_o, spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i, spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i, pcbrev_i => pcbrev_i,
button1_n_i => button1_n_i,
ddr_dma_clk_i => clk_sys_62m5, ddr_a_o => ddr_a_o,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
clk_62m5_sys_o => clk_sys_62m5, ddr_ck_n_o => ddr_ck_n_o,
rst_62m5_sys_n_o => rst_sys_62m5_n, ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
-- Everything is handled by the carrier. ddr_dq_b => ddr_dq_b,
app_wb_o => gn_wb_out, ddr_ldm_o => ddr_ldm_o,
app_wb_i => gn_wb_in ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o
); );
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end rtl; end architecture arch;
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