Single access DDR controller test firmware.

398a0c79 · Matthieu Cattin · 475d238d · 398a0c79 · 398a0c79 · 398a0c79
Commit 398a0c79 authored Jul 26, 2011 by Matthieu Cattin
4 changed files
--- a/hdl/test_ddr/rtl/Manifest.py
+++ b/hdl/test_ddr/rtl/Manifest.py
-files = ["spec_ddr_test_top.vhd",
+files = ["spec_ddr_test.vhd",
         "gpio_regs.vhd"]

-modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
-                    "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl/spec/rtl"]}
+modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/branches/xilinx_fifo/gn4124core/rtl",
+                    "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
+                    "http://svn.ohwr.org/gn4124-core/branches/xilinx_fifo/spec/ip_cores"]}
+
+fetchto = "../ip_cores"
--- a/hdl/test_ddr/rtl/spec_ddr_test.vhd
+++ b/hdl/test_ddr/rtl/spec_ddr_test.vhd
@@ -82,8 +82,12 @@ entity spec_ddr_test is
      VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready

      -- Font panel LEDs
-      LED_RED   : out std_logic;
-      LED_GREEN : out std_logic;
+      LED_RED_O   : out std_logic;
+      LED_GREEN_O : out std_logic;
+
+      -- Auxiliary pins
+      AUX_LEDS_O    : out std_logic_vector(3 downto 0);
+      AUX_BUTTONS_I : in  std_logic_vector(1 downto 0);

      -- DDR3 interface
      DDR3_CAS_N   : out   std_logic;
@@ -204,7 +208,6 @@ architecture rtl of spec_ddr_test is
    generic(
      g_MEMCLK_PERIOD      : integer := 3200;               -- in ps
      g_RST_ACT_LOW        : integer := 1;                  -- 1=active low
-      g_INPUT_CLK_TYPE     : string  := "SINGLE_ENDED";
      g_SIMULATION         : string  := "FALSE";
      g_CALIB_SOFT_IP      : string  := "TRUE";
      g_MEM_ADDR_ORDER     : string  := "ROW_BANK_COLUMN";  -- BANK_ROW_COLUMN or ROW_BANK_COLUMN
@@ -213,8 +216,10 @@ architecture rtl of spec_ddr_test is
      g_MEM_BANKADDR_WIDTH : integer := 3;
      g_P0_MASK_SIZE       : integer := 4;
      g_P0_DATA_PORT_SIZE  : integer := 32;
+      g_P0_BYTE_ADDR_WIDTH : integer := 30;
      g_P1_MASK_SIZE       : integer := 4;
-      g_P1_DATA_PORT_SIZE  : integer := 32
+      g_P1_DATA_PORT_SIZE  : integer := 32;
+      g_P1_BYTE_ADDR_WIDTH : integer := 30
      );

    port(
@@ -246,20 +251,20 @@ architecture rtl of spec_ddr_test is
      wb0_cyc_i   : in  std_logic;
      wb0_stb_i   : in  std_logic;
      wb0_we_i    : in  std_logic;
-      wb0_addr_i  : in  std_logic_vector(29 downto 0);
+      wb0_addr_i  : in  std_logic_vector(g_P0_BYTE_ADDR_WIDTH - 3 downto 0);
      wb0_data_i  : in  std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
      wb0_data_o  : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
      wb0_ack_o   : out std_logic;
      wb0_stall_o : out std_logic;

      wb1_clk_i   : in  std_logic;
-      wb1_sel_i   : in  std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
+      wb1_sel_i   : in  std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
      wb1_cyc_i   : in  std_logic;
      wb1_stb_i   : in  std_logic;
      wb1_we_i    : in  std_logic;
-      wb1_addr_i  : in  std_logic_vector(29 downto 0);
-      wb1_data_i  : in  std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
-      wb1_data_o  : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
+      wb1_addr_i  : in  std_logic_vector(g_P1_BYTE_ADDR_WIDTH - 3 downto 0);
+      wb1_data_i  : in  std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
+      wb1_data_o  : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
      wb1_ack_o   : out std_logic;
      wb1_stall_o : out std_logic
      );
@@ -285,22 +290,6 @@ architecture rtl of spec_ddr_test is
      );
  end component gpio_regs;

-  component monostable
-    generic(
-      g_INPUT_POLARITY  : std_logic := '1';    --! trigger_i polarity
-                                               --! ('0'=negative, 1=positive)
-      g_OUTPUT_POLARITY : std_logic := '1';    --! pulse_o polarity
-                                               --! ('0'=negative, 1=positive)
-      g_OUTPUT_RETRIG   : boolean   := false;  --! Retriggerable output monostable
-      g_OUTPUT_LENGTH   : natural   := 1       --! pulse_o lenght (in clk_i ticks)
-      );
-    port (
-      rst_n_i   : in  std_logic;               --! Reset (active low)
-      clk_i     : in  std_logic;               --! Clock
-      trigger_i : in  std_logic;               --! Trigger input pulse
-      pulse_o   : out std_logic                --! Monostable output pulse
-      );
-  end component monostable;

  ------------------------------------------------------------------------------
  -- Constants declaration
@@ -346,7 +335,7 @@ architecture rtl of spec_ddr_test is
  signal wb_we      : std_logic;
  signal wb_ack     : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
  signal spi_wb_adr : std_logic_vector(4 downto 0);
-  signal ddr_wb_adr : std_logic_vector(29 downto 0);
+  signal ddr_wb_adr : std_logic_vector(26 downto 0);

  -- DMA wishbone bus
  signal dma_adr     : std_logic_vector(31 downto 0);
@@ -359,7 +348,7 @@ architecture rtl of spec_ddr_test is
  signal dma_ack     : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
  signal dma_stall   : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
  signal ram_we      : std_logic_vector(0 downto 0);
-  signal ddr_dma_adr : std_logic_vector(29 downto 0);
+  signal ddr_dma_adr : std_logic_vector(27 downto 0);

  -- Interrupts stuff
  signal irq_sources       : std_logic_vector(1 downto 0);
@@ -376,6 +365,11 @@ architecture rtl of spec_ddr_test is
  -- DDR3
  signal ddr3_calib_done : std_logic;

+  -- LED
+  signal led_cnt1 : unsigned(22 downto 0);
+  signal led_cnt2 : unsigned(24 downto 0);
+  signal led_en   : std_logic;
+

 begin

@@ -433,6 +427,7 @@ begin
      O => sys_clk_200,
      I => sys_clk_200_buf);

+  -- Note that the IBUFG have to be removed from the generated ddr core (memc3_infrastructure.vhd)
  cmp_ddr_clk_buf : BUFG
    port map (
      O => ddr_clk,
@@ -572,23 +567,40 @@ begin
               & sys_clk_pll_locked
               & p2l_pll_locked;

-  gen_irq_led : for I in 0 to 1 generate
-    cmp_irq_led : monostable
-      generic map(
-        g_INPUT_POLARITY  => '1',
-        g_OUTPUT_POLARITY => '1',
-        g_OUTPUT_RETRIG   => false,
-        g_OUTPUT_LENGTH   => 5000000)
-      port map(
-        rst_n_i   => L_RST_N,
-        clk_i     => sys_clk_50,
-        trigger_i => irq_sources(I),
-        pulse_o   => irq_sources_2_led(I));
-  end generate gen_irq_led;
-
-
-  LED_RED   <= gpio_led_ctrl(0) or irq_sources_2_led(0);
-  LED_GREEN <= gpio_led_ctrl(1) or irq_sources_2_led(1);
+  p_led_mono_1 : process (L_RST_N, sys_clk_50)
+  begin
+    if L_RST_N = '0' then
+      led_cnt1 <= (others => '0');
+    elsif rising_edge(sys_clk_50) then
+      if irq_sources(0) = '1' then
+        led_cnt1             <= (others => '1');
+        irq_sources_2_led(0) <= '1';
+      elsif led_cnt1 = 0 then
+        irq_sources_2_led(0) <= '0';
+      else
+        led_cnt1 <= led_cnt1 - 1;
+      end if;
+    end if;
+  end process p_led_mono_1;
+
+  p_led_cnt : process (L_RST_N, sys_clk_50)
+  begin
+    if L_RST_N = '0' then
+      led_cnt2 <= (others => '1');
+      led_en   <= '1';
+    elsif rising_edge(sys_clk_50) then
+      led_cnt2 <= led_cnt2 - 1;
+      led_en   <= led_cnt2(24);
+    end if;
+  end process p_led_cnt;
+
+  LED_RED_O   <= gpio_led_ctrl(0) or irq_sources_2_led(0);
+  LED_GREEN_O <= gpio_led_ctrl(1) or led_en;
+
+  AUX_LEDS_O(0) <= not(led_en);
+  AUX_LEDS_O(1) <= not(sys_clk_pll_locked);
+  AUX_LEDS_O(2) <= not(p2l_pll_locked);
+  AUX_LEDS_O(3) <= not(ddr3_calib_done);

  ------------------------------------------------------------------------------
  -- Interrupt stuff
@@ -602,9 +614,12 @@ begin
  ------------------------------------------------------------------------------
  cmp_ddr_ctrl : ddr3_ctrl
    generic map(
-      g_MEMCLK_PERIOD => 3000,
-      g_SIMULATION    => g_SIMULATION,
-      g_CALIB_SOFT_IP => g_CALIB_SOFT_IP)
+      g_MEMCLK_PERIOD      => 3000,
+      g_SIMULATION         => g_SIMULATION,
+      g_CALIB_SOFT_IP      => g_CALIB_SOFT_IP,
+      g_P0_MASK_SIZE       => 4,
+      g_P0_DATA_PORT_SIZE  => 32,
+      g_P0_BYTE_ADDR_WIDTH => 30)
    port map (
      clk_i   => ddr_clk,
      rst_n_i => L_RST_N,
@@ -631,15 +646,15 @@ begin
      ddr3_rzq_b    => DDR3_RZQ,
      ddr3_zio_b    => DDR3_ZIO,

-      wb0_clk_i   => sys_clk_50,              --'0',
-      wb0_sel_i   => "1111",
-      wb0_cyc_i   => wb_cyc(2),               --'0',
-      wb0_stb_i   => wb_stb,                  --'0',
-      wb0_we_i    => wb_we,                   --'0',
-      wb0_addr_i  => ddr_wb_adr,              --X"0000000" & "00",
-      wb0_data_i  => wb_dat_o,                --X"00000000",
-      wb0_data_o  => wb_dat_i(95 downto 64),  --open,
-      wb0_ack_o   => wb_ack(2),               --open,
+      wb0_clk_i   => sys_clk_50,        --'0',
+      wb0_sel_i   => X"F",
+      wb0_cyc_i   => '0',  --wb_cyc(2),               --'0',
+      wb0_stb_i   => '0',  --wb_stb,                  --'0',
+      wb0_we_i    => '0',  --wb_we,                   --'0',
+      wb0_addr_i  => X"0000000",
+      wb0_data_i  => X"00000000",  --wb_dat_o,                --X"00000000",
+      wb0_data_o  => open,  --wb_dat_i(95 downto 64),  --open,
+      wb0_ack_o   => open,  --wb_ack(2),               --open,
      wb0_stall_o => open,

      wb1_clk_i   => sys_clk_50,
@@ -647,18 +662,12 @@ begin
      wb1_cyc_i   => dma_cyc,
      wb1_stb_i   => dma_stb,
      wb1_we_i    => dma_we,
-      wb1_addr_i  => ddr_dma_adr,
+      wb1_addr_i  => dma_adr(27 downto 0),
      wb1_data_i  => dma_dat_o,
      wb1_data_o  => dma_dat_i,
      wb1_ack_o   => dma_ack,
      wb1_stall_o => dma_stall);

-  -- 32-bit word to byte address
-  ddr_wb_adr <= "0000000000" & wb_adr & "00";
-
-  -- 32-bit word to byte address
-  ddr_dma_adr <= dma_adr(27 downto 0) & "00";
-
  ------------------------------------------------------------------------------
  -- Assign unused outputs
  ------------------------------------------------------------------------------

--- a/hdl/test_ddr/spec_ddr_test.ucf
+++ b/hdl/test_ddr/spec_ddr_test.ucf
-#---------------------------------------------------------------------------------------------
+#===============================================================================
 # The IO Location Constraints
-#---------------------------------------------------------------------------------------------
-
-NET "CLK_20M_VCXO_I" LOC = H12;
-NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
-
-#NET "EN_FB_RX" LOC = D5;
-#NET "EN_FB_RX" IOSTANDARD = "LVCMOS25";
-#NET "EN_FB_TX" LOC = E5;
-#NET "EN_FB_TX" IOSTANDARD = "LVCMOS25";
-#NET "FB_N" LOC = A18;
-#NET "FB_N" IOSTANDARD = "LVDS_25";
-#NET "FB_P" LOC = B18;
-#NET "FB_P" IOSTANDARD = "LVCMOS25";
+#===============================================================================
+
+#----------------------------------------
+# Clock inputs
+#----------------------------------------
+NET "clk_20m_vcxo_i" LOC = H12; # CLK25_VCXO
+NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
+
 #NET "clk_125m_pllref_n_i" LOC = F10;
 #NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
-
 #NET "clk_125m_pllref_p_i" LOC = G9;
 #NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";

-#NET "LA31_N" LOC = C18;
-#NET "LA31_N" IOSTANDARD = "LVCMOS25";
-#NET "LA31_P" LOC = D17;
-#NET "LA31_P" IOSTANDARD = "LVCMOS25";
-#NET "LA32_N" LOC = A20;
-#NET "LA32_N" IOSTANDARD = "LVCMOS25";
-#NET "LA32_P" LOC = B20;
-#NET "LA32_P" IOSTANDARD = "LVCMOS25";
-#NET "LA33_N" LOC = A19;
-#NET "LA33_N" IOSTANDARD = "LVCMOS25";
-#NET "LA33_P" LOC = C19;
-#NET "LA33_P" IOSTANDARD = "LVCMOS25";
-#NET "OE_SI57X" LOC = H13;
-#NET "OE_SI57X" IOSTANDARD = "LVCMOS25";
-#NET "PG_C2M" LOC = B2;
-#NET "PG_C2M" IOSTANDARD = "LVCMOS25";
-#NET "dac_cs1_n_o" LOC = A3;
-#NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
-
-#NET "dac_cs2_n_o" LOC = B3;
-#NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
-
-#NET "dac_clr_n_o" LOC = F7;
-#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
-
-#NET "dac_din_o" LOC = C4;
-#NET "dac_din_o" IOSTANDARD = "LVCMOS25";
-
-#NET "dac_sclk_o" LOC = A4;
-#NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
-
-#NET "SI57X_CLK_N" LOC = F15;
-#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
-#NET "SI57X_CLK_P" LOC = F14;
-#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
-#NET "TCK_TO_FMC" LOC = G8;
-#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
-#NET "TDI_TO_FMC" LOC = H11;
-#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
-#NET "THERMO_ID" LOC = D4;
-#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
-#NET "TMS_TO_FMC" LOC = H10;
-#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
-#NET "PRSNT_M2C_L" LOC = A2;
-#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
-#NET "SFP_TX_FAULT" LOC = A17;
+#----------------------------------------
+# SFP slot
+# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
+#----------------------------------------
+#NET "SFPRX_123_N" LOC = C15;
+#NET "SFPRX_123_N" IOSTANDARD = "LVCMOS25";
+#NET "SFPRX_123_P" LOC = D15;
+#NET "SFPRX_123_P" IOSTANDARD = "LVCMOS25";
+#NET "SFPTX_123_N" LOC = A16;
+#NET "SFPTX_123_N" IOSTANDARD = "LVCMOS25";
+#NET "SFPTX_123_P" LOC = B16;
+#NET "SFPTX_123_P" IOSTANDARD = "LVCMOS25";
+#NET "SFP_TX_FAULT" LOC = B18;
 #NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
-#NET "SFP_TX_DISABLE" LOC = C17;
+#NET "SFP_TX_DISABLE" LOC = F17;
 #NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
 #NET "SFP_LOS" LOC = D18;
 #NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
-#NET "TRST_TO_FMC" LOC = E6;
-#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
-#NET "CLK0_M2C_P" LOC = E16;
-#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
-
-
-#NET "scl0_b" LOC = C5;
-#NET "scl0_b" IOSTANDARD = "LVCMOS25";
-
-#NET "FPGA_SCL" LOC = C5;
-#NET "FPGA_SCL" IOSTANDARD = "LVCMOS25";
-
-#NET "sda0_b" LOC = F8;
-#NET "sda0_b" IOSTANDARD = "LVCMOS25";
-
-#NET "FPGA_SDA" LOC = F8;
-#NET "FPGA_SDA" IOSTANDARD = "LVCMOS25";
-
-#NET "TDO_FROM_FMC" LOC = F9;
-#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
-#NET "CLK0_M2C_N" LOC = F16;
-#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
-#NET "SFP_MOD_DEF1" LOC = F17;
+#NET "SFP_MOD_DEF1" LOC = C17;
 #NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
 #NET "SFP_MOD_DEF0" LOC = G15;
 #NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
@@ -101,6 +40,35 @@ NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
 #NET "SFP_RATE_SELECT" LOC = H14;
 #NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";

+#----------------------------------------
+# DAC interface (for VCXO)
+#----------------------------------------
+#NET "PLL25DAC1_SYNC_N" LOC = A3;
+#NET "PLL25DAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
+#NET "PLL25DAC2_SYNC_N" LOC = B3;
+#NET "PLL25DAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
+#NET "PLL25DAC_DIN" LOC = C4;
+#NET "PLL25DAC_DIN" IOSTANDARD = "LVCMOS25";
+#NET "PLL25DAC_SCLK" LOC = A4;
+#NET "PLL25DAC_SCLK" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# 1-wire thermometer w/ ID
+#----------------------------------------
+#NET "THERMO_ID" LOC = D4;
+#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# I2C interface
+#----------------------------------------
+#NET "FPGA_SCL" LOC = F7;
+#NET "FPGA_SCL" IOSTANDARD = "LVCMOS25";
+#NET "FPGA_SDA" LOC = F8;
+#NET "FPGA_SDA" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# GN4124 interface
+#----------------------------------------
 NET "L_RST_N" LOC = N20;
 NET "L_RST_N" IOSTANDARD = "LVCMOS18";
 NET "L2P_CLKN" LOC = K22;
@@ -131,7 +99,7 @@ NET "P2L_DFRAME" LOC = J22;
 NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
 NET "P2L_RDY" LOC = J16;
 NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
-NET "P2L_VALID" LOC = N22;
+NET "P2L_VALID" LOC = L19;
 NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
 NET "P_RD_D_RDY[0]" LOC = N16;
 NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
@@ -223,170 +191,229 @@ NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
 NET "GPIO[1]" LOC = AB19;
 NET "GPIO[1]" IOSTANDARD = "LVCMOS25";

-#NET "CLK1_M2C_P" LOC = L20;
-#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
-#NET "CLK1_M2C_N" LOC = L22;
-#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
+#----------------------------------------
+# FMC slot
+#----------------------------------------
+#NET "ext_trigger_n_i" LOC = AB13; # LA17_N
+#NET "ext_trigger_n_i" IOSTANDARD = "LVDS_25";
+#NET "ext_trigger_p_i" LOC = Y13; # LA17_P
+#NET "ext_trigger_p_i" IOSTANDARD = "LVDS_25";
+
+# dco_p and dco_n are swapped compared to the FMC ADC schematics
+# this is to be coherent in the hdl design
+#NET "adc_dco_n_i" LOC = AB11; # LA00_N
+#NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
+#NET "adc_dco_p_i" LOC = Y11; # LA00_P
+#NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
+
+# fr_p and fr_n are swapped compared to the FMC ADC schematics
+# this is to be coherent in the hdl design
+#NET "adc_fr_n_i" LOC = AB12; # LA01_N
+#NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
+#NET "adc_fr_p_i" LOC = AA12; # LA01_P
+#NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
+
+#NET "adc_outa_n_i[0]" LOC = AB4; # LA14_N
+#NET "adc_outa_n_i[0]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_p_i[0]" LOC = AA4; # LA14_P
+#NET "adc_outa_p_i[0]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_n_i[0]" LOC = W11; # LA15_N
+#NET "adc_outb_n_i[0]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_p_i[0]" LOC = V11; # LA15_P
+#NET "adc_outb_p_i[0]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_n_i[1]" LOC = Y12; # LA16_N
+#NET "adc_outa_n_i[1]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_p_i[1]" LOC = W12; # LA16_P
+#NET "adc_outa_p_i[1]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_n_i[1]" LOC = AB9; # LA13_N
+#NET "adc_outb_n_i[1]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_p_i[1]" LOC = Y9; # LA13_P
+#NET "adc_outb_p_i[1]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_n_i[2]" LOC = AB8; # LA10_N
+#NET "adc_outa_n_i[2]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_p_i[2]" LOC = AA8; # LA10_P
+#NET "adc_outa_p_i[2]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_n_i[2]" LOC = AB7; # LA09_N
+#NET "adc_outb_n_i[2]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_p_i[2]" LOC = Y7; # LA09_P
+#NET "adc_outb_p_i[2]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_n_i[3]" LOC = V9; # LA07_N
+#NET "adc_outa_n_i[3]" IOSTANDARD = "LVDS_25";
+#NET "adc_outa_p_i[3]" LOC = U9; # LA07_P
+#NET "adc_outa_p_i[3]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_n_i[3]" LOC = AB6; # LA05_N
+#NET "adc_outb_n_i[3]" IOSTANDARD = "LVDS_25";
+#NET "adc_outb_p_i[3]" LOC = AA6; # LA05_P
+#NET "adc_outb_p_i[3]" IOSTANDARD = "LVDS_25";
+
+#NET "spi_din_i" LOC = T15; # LA25_P
+#NET "spi_din_i" IOSTANDARD = "LVCMOS25";
+#NET "spi_dout_o" LOC = C18; # LA31_N
+#NET "spi_dout_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_sck_o" LOC = D17; # LA31_P
+#NET "spi_sck_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_cs_adc_n_o" LOC = V17; # LA30_P
+#NET "spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_cs_dac1_n_o" LOC = B20; # LA32_P
+#NET "spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_cs_dac2_n_o" LOC = A20; # LA32_N
+#NET "spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_cs_dac3_n_o" LOC = C19; # LA33_P
+#NET "spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
+#NET "spi_cs_dac4_n_o" LOC = A19; # LA33_N
+#NET "spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_dac_clr_n_o" LOC = W18; # LA30_N
+#NET "gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_led_power_o" LOC = W15; # LA28_N
+#NET "gpio_led_power_o" IOSTANDARD = "LVCMOS25";
+#NET "gpio_led_trigger_o" LOC = Y16; # LA28_P
+#NET "gpio_led_trigger_o" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_ssr_ch1_o[0]" LOC = Y17; # LA26_P
+#NET "gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[1]" LOC = AB17; # LA26_N
+#NET "gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[2]" LOC = AB18; # LA27_N
+#NET "gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[3]" LOC = U15; # LA25_N
+#NET "gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[4]" LOC = W14; # LA24_P
+#NET "gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[5]" LOC = Y14; # LA24_N
+#NET "gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch1_o[6]" LOC = W17; # LA29_P
+#NET "gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_ssr_ch2_o[0]" LOC = R11; # LA20_P
+#NET "gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[1]" LOC = AB15; # LA19_N
+#NET "gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[2]" LOC = R13; # LA22_P
+#NET "gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[3]" LOC = T14; # LA22_N
+#NET "gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[4]" LOC = V13; # LA21_P
+#NET "gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[5]" LOC = AA18; # LA27_P
+#NET "gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch2_o[6]" LOC = W13; # LA21_N
+#NET "gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_ssr_ch3_o[0]" LOC = R9; # LA08_P
+#NET "gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[1]" LOC = R8; # LA08_N
+#NET "gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[2]" LOC = T10; # LA12_P
+#NET "gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[3]" LOC = U10; # LA12_N
+#NET "gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[4]" LOC = W10; # LA11_P
+#NET "gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[5]" LOC = Y10; # LA11_N
+#NET "gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch3_o[6]" LOC = T11; # LA20_N
+#NET "gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_ssr_ch4_o[0]" LOC = W6; # LA02_P
+#NET "gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[1]" LOC = Y6; # LA02_N
+#NET "gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[2]" LOC = V7; # LA03_P
+#NET "gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[3]" LOC = W8; # LA03_N
+#NET "gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[4]" LOC = T8; # LA04_P
+#NET "gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[5]" LOC = Y5; # LA06_P
+#NET "gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
+#NET "gpio_ssr_ch4_o[6]" LOC = U8; # LA04_N
+#NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
+
+#NET "gpio_si570_oe_o" LOC = AB5; # LA06_N
+#NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
+
+#NET "si570_thermo_scl_b" LOC = U12; # LA18_N
+#NET "si570_thermo_scl_b" IOSTANDARD = "LVCMOS25";
+#NET "si570_thermo_sda_b" LOC = T12; # LA18_P
+#NET "si570_thermo_sda_b" IOSTANDARD = "LVCMOS25";
+
+#NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
+#NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# FMC slot (unused pins)
+#----------------------------------------
+#NET "PG_C2M" LOC = AA14;
+#NET "PG_C2M" IOSTANDARD = "LVCMOS25";

-#NET "LA00_N" LOC = AB11;
-#NET "LA00_N" IOSTANDARD = "LVCMOS25";
-#NET "LA00_P" LOC = Y11;
-#NET "LA00_P" IOSTANDARD = "LVCMOS25";
-#NET "LA01_N" LOC = AB12;
-#NET "LA01_N" IOSTANDARD = "LVCMOS25";
-#NET "LA01_P" LOC = AA12;
-#NET "LA01_P" IOSTANDARD = "LVCMOS25";
-
-#NET "sda1_b" LOC = Y6;
-#NET "sda1_b" IOSTANDARD = "LVCMOS25";
-#NET "scl1_b" LOC = W6;
-#NET "scl1_b" IOSTANDARD = "LVCMOS25";
-
-#NET "LA02_N" LOC = Y6;
-#NET "LA02_N" IOSTANDARD = "LVCMOS25";
-#NET "LA02_P" LOC = W6;
-#NET "LA02_P" IOSTANDARD = "LVCMOS25";
-
-#NET "LA03_N" LOC = W8;
-#NET "LA03_N" IOSTANDARD = "LVCMOS25";
-#NET "LA03_P" LOC = V7;
-#NET "LA03_P" IOSTANDARD = "LVCMOS25";
-#NET "LA04_N" LOC = U8;
-#NET "LA04_N" IOSTANDARD = "LVCMOS25";
-#NET "LA04_P" LOC = T8;
-#NET "LA04_P" IOSTANDARD = "LVCMOS25";
-#NET "LA05_N" LOC = AB6;
-#NET "LA05_N" IOSTANDARD = "LVCMOS25";
-#NET "LA05_P" LOC = AA6;
-#NET "LA05_P" IOSTANDARD = "LVCMOS25";
-#NET "LA06_N" LOC = AB5;
-#NET "LA06_N" IOSTANDARD = "LVCMOS25";
-#NET "LA06_P" LOC = Y5;
-#NET "LA06_P" IOSTANDARD = "LVCMOS25";
-#NET "LA07_N" LOC = V9;
-#NET "LA07_N" IOSTANDARD = "LVCMOS25";
-#NET "LA07_P" LOC = U9;
-#NET "LA07_P" IOSTANDARD = "LVCMOS25";
-#NET "LA08_N" LOC = R8;
-#NET "LA08_N" IOSTANDARD = "LVCMOS25";
-#NET "LA08_P" LOC = R9;
-#NET "LA08_P" IOSTANDARD = "LVCMOS25";
-#NET "LA09_N" LOC = AB7;
-#NET "LA09_N" IOSTANDARD = "LVCMOS25";
-#NET "LA09_P" LOC = Y7;
-#NET "LA09_P" IOSTANDARD = "LVCMOS25";
-#NET "LA10_N" LOC = AB8;
-#NET "LA10_N" IOSTANDARD = "LVCMOS25";
-#NET "LA10_P" LOC = AA8;
-#NET "LA10_P" IOSTANDARD = "LVCMOS25";
-#NET "LA11_N" LOC = Y10;
-#NET "LA11_N" IOSTANDARD = "LVCMOS25";
-#NET "LA11_P" LOC = W10;
-#NET "LA11_P" IOSTANDARD = "LVCMOS25";
-#NET "LA12_N" LOC = U10;
-#NET "LA12_N" IOSTANDARD = "LVCMOS25";
-#NET "LA12_P" LOC = T10;
-#NET "LA12_P" IOSTANDARD = "LVCMOS25";
-#NET "LA13_N" LOC = AB9;
-#NET "LA13_N" IOSTANDARD = "LVCMOS25";
-#NET "LA13_P" LOC = Y9;
-#NET "LA13_P" IOSTANDARD = "LVCMOS25";
-#NET "LA14_N" LOC = AB4;
-#NET "LA14_N" IOSTANDARD = "LVCMOS25";
-#NET "LA14_P" LOC = AA4;
-#NET "LA14_P" IOSTANDARD = "LVCMOS25";
-#NET "LA15_N" LOC = W11;
-#NET "LA15_N" IOSTANDARD = "LVCMOS25";
-#NET "LA15_P" LOC = V11;
-#NET "LA15_P" IOSTANDARD = "LVCMOS25";
-#NET "LA16_N" LOC = AB15;
-#NET "LA16_N" IOSTANDARD = "LVCMOS25";
-#NET "LA16_P" LOC = Y15;
-#NET "LA16_P" IOSTANDARD = "LVCMOS25";
-#NET "LA17_N" LOC = AB13;
-#NET "LA17_N" IOSTANDARD = "LVCMOS25";
-#NET "LA17_P" LOC = Y13;
-#NET "LA17_P" IOSTANDARD = "LVCMOS25";
-#NET "LA18_N" LOC = U12;
-#NET "LA18_N" IOSTANDARD = "LVCMOS25";
-#NET "LA18_P" LOC = T12;
-#NET "LA18_P" IOSTANDARD = "LVCMOS25";
-#NET "LA19_N" LOC = Y12;
-#NET "LA19_N" IOSTANDARD = "LVCMOS25";
-#NET "LA19_P" LOC = W12;
+#NET "LA19_P" LOC = Y15;
 #NET "LA19_P" IOSTANDARD = "LVCMOS25";
-#NET "LA20_N" LOC = T11;
-#NET "LA20_N" IOSTANDARD = "LVCMOS25";
-#NET "LA20_P" LOC = R11;
-#NET "LA20_P" IOSTANDARD = "LVCMOS25";
-#NET "LA21_N" LOC = W13;
-#NET "LA21_N" IOSTANDARD = "LVCMOS25";
-#NET "LA21_P" LOC = V13;
-#NET "LA21_P" IOSTANDARD = "LVCMOS25";
-#NET "LA22_N" LOC = T14;
-#NET "LA22_N" IOSTANDARD = "LVCMOS25";
-#NET "LA22_P" LOC = R13;
-#NET "LA22_P" IOSTANDARD = "LVCMOS25";
 #NET "LA23_N" LOC = AB16;
 #NET "LA23_N" IOSTANDARD = "LVCMOS25";
 #NET "LA23_P" LOC = AA16;
 #NET "LA23_P" IOSTANDARD = "LVCMOS25";
-#NET "LA24_N" LOC = Y14;
-#NET "LA24_N" IOSTANDARD = "LVCMOS25";
-#NET "LA24_P" LOC = W14;
-#NET "LA24_P" IOSTANDARD = "LVCMOS25";
-#NET "LA25_N" LOC = U15;
-#NET "LA25_N" IOSTANDARD = "LVCMOS25";
-#NET "LA25_P" LOC = T15;
-#NET "LA25_P" IOSTANDARD = "LVCMOS25";
-#NET "LA26_N" LOC = AB17;
-#NET "LA26_N" IOSTANDARD = "LVCMOS25";
-#NET "LA26_P" LOC = Y17;
-#NET "LA26_P" IOSTANDARD = "LVCMOS25";
-#NET "LA27_N" LOC = AB18;
-#NET "LA27_N" IOSTANDARD = "LVCMOS25";
-#NET "LA27_P" LOC = AA18;
-#NET "LA27_P" IOSTANDARD = "LVCMOS25";
-#NET "LA28_N" LOC = W15;
-#NET "LA28_N" IOSTANDARD = "LVCMOS25";
-#NET "LA28_P" LOC = Y16;
-#NET "LA28_P" IOSTANDARD = "LVCMOS25";
 #NET "LA29_N" LOC = Y18;
 #NET "LA29_N" IOSTANDARD = "LVCMOS25";
-#NET "LA29_P" LOC = W17;
-#NET "LA29_P" IOSTANDARD = "LVCMOS25";
-#NET "LA30_N" LOC = W18;
-#NET "LA30_N" IOSTANDARD = "LVCMOS25";
-#NET "LA30_P" LOC = V17;
-#NET "LA30_P" IOSTANDARD = "LVCMOS25";
-
-#NET "SI57X_SCL" LOC = AA14;
+
+#NET "TDO_FROM_FMC" LOC = F9;
+#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
+#NET "TCK_TO_FMC" LOC = G8;
+#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
+#NET "TDI_TO_FMC" LOC = H11;
+#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
+#NET "TMS_TO_FMC" LOC = H10;
+#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
+#NET "TRST_TO_FMC" LOC = E6;
+#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
+
+#NET "CLK0_M2C_P" LOC = E16;
+#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
+#NET "CLK0_M2C_N" LOC = F16;
+#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
+#NET "CLK1_M2C_P" LOC = L20;
+#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
+#NET "CLK1_M2C_N" LOC = L22;
+#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
+
+#----------------------------------------
+# SI57x interface
+#----------------------------------------
+#NET "SI57X_SCL" LOC = A18;
 #NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
-#NET "SI57X_SDA" LOC = AB14;
+#NET "SI57X_SDA" LOC = A17;
 #NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";
+#NET "SI57X_OE" LOC = H13;
+#NET "SI57X_OE" IOSTANDARD = "LVCMOS25";
+#NET "SI57X_CLK_N" LOC = F15;
+#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
+#NET "SI57X_CLK_P" LOC = F14;
+#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";

-NET "LED_RED" LOC = T6;
-NET "LED_RED" IOSTANDARD = "LVCMOS15";
-NET "LED_GREEN" LOC = Y3;
-NET "LED_GREEN" IOSTANDARD = "LVCMOS15";
-
-#NET "PCB_VER[0]" LOC = P5;
-#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[1]" LOC = P4;
-#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[2]" LOC = AA2;
-#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[3]" LOC = AA1;
-#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[4]" LOC = N6;
-#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[5]" LOC = N7;
-#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[6]" LOC = U4;
-#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
-#NET "PCB_VER[7]" LOC = T4;
-#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";
-
+#----------------------------------------
+# Carrier front panel LEDs
+#----------------------------------------
+NET "led_red_o" LOC = D5;
+NET "led_red_o" IOSTANDARD = "LVCMOS25";
+NET "led_green_o" LOC = E5;
+NET "led_green_o" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# PCB version number (coded with resistors)
+#----------------------------------------
+#NET "pcb_ver_i[0]" LOC = P5;
+#NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
+#NET "pcb_ver_i[1]" LOC = P4;
+#NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
+#NET "pcb_ver_i[2]" LOC = AA2;
+#NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
+#NET "pcb_ver_i[3]" LOC = AA1;
+#NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
+
+#----------------------------------------
+# DDR3 interface
+#----------------------------------------
 NET "DDR3_CAS_N" LOC = M4;
 NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
 NET "DDR3_CK_N" LOC = K3;
@@ -489,16 +516,41 @@ NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
 NET "DDR3_DQ[15]" LOC = Y1;
 NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";

-#---------------------------------------------------------------------------------------------
+#----------------------------------------
+# UART
+#----------------------------------------
+#NET "UART_TXD" LOC = A2; # FPGA input
+#NET "UART_TXD" IOSTANDARD = "LVCMOS25";
+#NET "UART_RXD" LOC = B2; # FPGA output
+#NET "UART_RXD" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# Buttons and LEDs
+#----------------------------------------
+NET "AUX_BUTTONS_I[0]" LOC = C22;
+NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
+NET "AUX_BUTTONS_I[1]" LOC = D21;
+NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
+NET "AUX_LEDS_O[0]" LOC = G19;
+NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
+NET "AUX_LEDS_O[1]" LOC = F20;
+NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
+NET "AUX_LEDS_O[2]" LOC = F18;
+NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
+NET "AUX_LEDS_O[3]" LOC = C20;
+NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
+
+
+#===============================================================================
 # IOBs
-#---------------------------------------------------------------------------------------------
+#===============================================================================
 INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
 INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;


-#---------------------------------------------------------------------------------------------
+#===============================================================================
 # Terminations
-#---------------------------------------------------------------------------------------------
+#===============================================================================

 # DDR3

@@ -509,18 +561,18 @@ NET "DDR3_UDQS_P"  IN_TERM = NONE;
 NET "DDR3_UDQS_N"  IN_TERM = NONE;


-#---------------------------------------------------------------------------------------------
+#===============================================================================
 # Clock constraints
-#---------------------------------------------------------------------------------------------
+#===============================================================================

 # GN4124

 NET "L_CLKp" TNM_NET = "l_clkp_grp";
-TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 10 ns HIGH 50%;
+TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 6.25 ns HIGH 50%;
 NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
-TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 10 ns HIGH 50%;
+TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 6.25 ns HIGH 50%;
 NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
-TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 10 ns HIGH 50%;
+TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 6.25 ns HIGH 50%;

 # System clock

@@ -529,13 +581,13 @@ TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i_grp" 50 ns HIGH 50%;

 # DDR3

-NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
 TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5"  3.0  ns HIGH 50 %;


-#---------------------------------------------------------------------------------------------
+#===============================================================================
 # False Path
-#---------------------------------------------------------------------------------------------
+#===============================================================================

 # GN4124

@@ -544,7 +596,6 @@ NET "cmp_gn4124_core/rst_*" TIG;

 # DDR3

-NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-NET "cmp_ddr_ctrl/cmp_ddr_controller/c3_pll_lock" TIG;
-NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
-
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/c3_pll_lock" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
--- a/hdl/test_ddr/syn/spec_ddr_test.xise
+++ b/hdl/test_ddr/syn/spec_ddr_test.xise
@@ -12,127 +12,14 @@
    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
  </header>

-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="../rtl/spec_ddr_test_top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../spec_top.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../rtl/gpio_regs.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/ddr_controller_bank3.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../../../monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-  </files>
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>

  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
@@ -163,6 +50,7 @@
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
@@ -177,7 +65,9 @@
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
@@ -193,7 +83,7 @@
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -228,10 +118,12 @@
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -239,11 +131,12 @@
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/spec_ddr_test_top.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_ddr_test|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/spec_ddr_test.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_ddr_test" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -258,10 +151,15 @@
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
@@ -269,6 +167,8 @@
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
@@ -298,10 +198,13 @@
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="TB_SPEC" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -315,14 +218,15 @@
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TB_SPEC_map.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TB_SPEC_timesim.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TB_SPEC_synthesis.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TB_SPEC_translate.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
@@ -340,7 +244,7 @@
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TB_SPEC" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -362,7 +266,8 @@
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TB_SPEC" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TB_SPEC" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -372,22 +277,27 @@
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TB_SPEC" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
@@ -395,7 +305,13 @@
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -409,6 +325,7 @@
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -419,17 +336,20 @@
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TB_SPEC|TEST" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_ddr_test" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
@@ -437,23 +357,118 @@
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-02-03T14:39:09" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6448C103253D74B476BBC45DADC60C83" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-12T10:43:38" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A4459BBB5563DB49840D3D7DB31402AB" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

-  <bindings/>
-
  <libraries/>

-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
+  <files>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../spec_ddr_test.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/ddr_ctrl_bank3.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb_single.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../rtl/spec_ddr_test.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../rtl/gpio_regs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation"/>
+    </file>
+  </files>
+
+  <bindings/>
+
+  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>

 </project>