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Simple PCIe FMC carrier SPEC
Commit 0c84cf8d authored by Federico Vaga's avatar Federico Vaga
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sw:drv: rename spi-gcore to spi-ocores 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 518a7e65
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Showing with 161 additions and 151 deletions
software/kernel/Kbuild
View file @ 0c84cf8d
......@@ -30,7 +30,7 @@ KBUILD_EXTRA_SYMBOLS += $(FMC_ABS)/drivers/fmc/Module.symvers
obj-m := spec-fmc-carrier.o
obj-m += gn412x-gpio.o
obj-m += gn412x-fcl.o
obj-m += spi-gcore.o
obj-m += spi-ocores.o
spec-fmc-carrier-objs := spec-core.o
spec-fmc-carrier-objs += spec-core-fpga.o
......
software/kernel/platform_data/spi_gcores.h → software/kernel/platform_data/spi-ocores.h
View file @ 0c84cf8d
......@@ -4,10 +4,10 @@
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#ifndef __GN412X_GPIO_H__
#define __GN412X_GPIO_H__
#ifndef __SPI_OCORES_PDATA_H__
#define __SPI_OCORES_PDATA_H__
struct spi_gcores_platform_data {
struct spi_ocores_platform_data {
unsigned int big_endian;
unsigned int clock_hz;
};
......
software/kernel/spi-gcore.c → software/kernel/spi-ocores.c
View file @ 0c84cf8d
......@@ -15,29 +15,31 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include "platform_data/spi_gcores.h"
#include "platform_data/spi-ocores.h"
#define SPI_OCORES_BUF_SIZE 4
#define SPI_OCORES_CS_MAX_N 8
#define SPI_GCORES_BUF_SIZE 4
/* SPI register */
#define SPI_GCORES_RX(x) (x * SPI_GCORES_BUF_SIZE)
#define SPI_GCORES_TX(x) (x * SPI_GCORES_BUF_SIZE)
#define SPI_GCORES_CTRL 0x10
#define SPI_GCORES_DIV 0x14
#define SPI_GCORES_CS 0x18
#define SPI_OCORES_RX(x) (x * SPI_OCORES_BUF_SIZE)
#define SPI_OCORES_TX(x) (x * SPI_OCORES_BUF_SIZE)
#define SPI_OCORES_CTRL 0x10
#define SPI_OCORES_DIV 0x14
#define SPI_OCORES_CS 0x18
/* SPI control register fields mask */
#define SPI_GCORES_CTRL_CHAR_LEN 0x007F
#define SPI_GCORES_CTRL_GO 0x0100 /* go/busy */
#define SPI_GCORES_CTRL_BUSY 0x0100 /* go/busy */
#define SPI_GCORES_CTRL_Rx_NEG 0x0200
#define SPI_GCORES_CTRL_Tx_NEG 0x0400
#define SPI_GCORES_CTRL_LSB 0x0800
#define SPI_GCORES_CTRL_IE 0x1000
#define SPI_GCORES_CTRL_ASS 0x2000
#define SPI_GCORES_FLAG_POLL BIT(0)
struct spi_gcores {
#define SPI_OCORES_CTRL_CHAR_LEN 0x007F
#define SPI_OCORES_CTRL_GO 0x0100 /* go/busy */
#define SPI_OCORES_CTRL_BUSY 0x0100 /* go/busy */
#define SPI_OCORES_CTRL_Rx_NEG 0x0200
#define SPI_OCORES_CTRL_Tx_NEG 0x0400
#define SPI_OCORES_CTRL_LSB 0x0800
#define SPI_OCORES_CTRL_IE 0x1000
#define SPI_OCORES_CTRL_ASS 0x2000
#define SPI_OCORES_FLAG_POLL BIT(0)
struct spi_ocores {
struct spi_master *master;
unsigned long flags;
void __iomem *mem;
......@@ -54,39 +56,39 @@ struct spi_gcores {
unsigned int cur_rx_len;
/* Register Access functions */
uint32_t (*read)(struct spi_gcores *sp, unsigned int reg);
void (*write)(struct spi_gcores *sp, unsigned int reg, uint32_t val);
uint32_t (*read)(struct spi_ocores *sp, unsigned int reg);
void (*write)(struct spi_ocores *sp, unsigned int reg, uint32_t val);
};
enum spi_gcores_type {
TYPE_GCORES = 0,
enum spi_ocores_type {
TYPE_OCORES = 0,
};
static inline uint32_t spi_gcores_ioread32(struct spi_gcores *sp,
static inline uint32_t spi_ocores_ioread32(struct spi_ocores *sp,
unsigned int reg)
{
return ioread32(sp->mem + reg);
}
static inline void spi_gcores_iowrite32(struct spi_gcores *sp,
static inline void spi_ocores_iowrite32(struct spi_ocores *sp,
unsigned int reg, uint32_t val)
{
iowrite32(val, sp->mem + reg);
}
static inline uint32_t spi_gcores_ioread32be(struct spi_gcores *sp,
static inline uint32_t spi_ocores_ioread32be(struct spi_ocores *sp,
unsigned int reg)
{
return ioread32be(sp->mem + reg);
}
static inline void spi_gcores_iowrite32be(struct spi_gcores *sp,
static inline void spi_ocores_iowrite32be(struct spi_ocores *sp,
unsigned int reg, uint32_t val)
{
iowrite32be(val, sp->mem + reg);
}
static inline struct spi_gcores *spi_gcoresdev_to_sp(struct spi_device *spi)
static inline struct spi_ocores *spi_ocoresdev_to_sp(struct spi_device *spi)
{
return spi_master_get_devdata(spi->master);
}
......@@ -94,7 +96,7 @@ static inline struct spi_gcores *spi_gcoresdev_to_sp(struct spi_device *spi)
/**
* Configure controller according to SPI device needs
*/
static int spi_gcores_setup(struct spi_device *spi)
static int spi_ocores_setup(struct spi_device *spi)
{
return 0;
}
......@@ -102,74 +104,74 @@ static int spi_gcores_setup(struct spi_device *spi)
/**
* Release resources used by the SPI device
*/
static void spi_gcores_cleanup(struct spi_device *spi)
static void spi_ocores_cleanup(struct spi_device *spi)
{
}
/**
* Configure controller
*/
static void spi_gcores_hw_xfer_config(struct spi_gcores *sp,
static void spi_ocores_hw_xfer_config(struct spi_ocores *sp,
uint32_t ctrl,
uint16_t divider)
{
ctrl &= ~SPI_GCORES_CTRL_GO; /* be sure to not start */
sp->write(sp, ctrl, SPI_GCORES_CTRL);
sp->write(sp, divider, SPI_GCORES_DIV);
ctrl &= ~SPI_OCORES_CTRL_GO; /* be sure to not start */
sp->write(sp, ctrl, SPI_OCORES_CTRL);
sp->write(sp, divider, SPI_OCORES_DIV);
}
/**
* Transmit data in FIFO
*/
static void spi_gcores_hw_xfer_go(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_go(struct spi_ocores *sp)
{
uint32_t ctrl;
ctrl = sp->read(sp, SPI_GCORES_CTRL);
ctrl |= SPI_GCORES_CTRL_GO;
sp->write(sp, ctrl, SPI_GCORES_CTRL);
ctrl = sp->read(sp, SPI_OCORES_CTRL);
ctrl |= SPI_OCORES_CTRL_GO;
sp->write(sp, ctrl, SPI_OCORES_CTRL);
}
/**
* Slave Select
*/
static void spi_gcores_hw_xfer_cs(struct spi_gcores *sp,
static void spi_ocores_hw_xfer_cs(struct spi_ocores *sp,
unsigned int cs,
unsigned int val)
{
uint32_t ss;
ss = sp->read(sp, SPI_GCORES_CS);
ss = sp->read(sp, SPI_OCORES_CS);
if (val)
ss |= BIT(cs);
else
ss &= ~BIT(cs);
sp->write(sp, ss, SPI_GCORES_CS);
sp->write(sp, ss, SPI_OCORES_CS);
}
/**
* Write a TX register
*/
static void spi_gcores_tx_set(struct spi_gcores *sp,
static void spi_ocores_tx_set(struct spi_ocores *sp,
unsigned int idx, uint32_t val)
{
if (WARN(idx > 3, "Invalid TX register index %d (min:0, max: 3). Possible data corruption\n",
idx))
return;
sp->write(sp, val, SPI_GCORES_TX(idx));
sp->write(sp, val, SPI_OCORES_TX(idx));
}
/**
* Read an RX register
*/
static uint32_t spi_gcores_rx_get(struct spi_gcores *sp, unsigned int idx)
static uint32_t spi_ocores_rx_get(struct spi_ocores *sp, unsigned int idx)
{
if (WARN(idx > 3, "Invalid RX register index %d (min:0, max: 3). Possible data corruption\n",
idx))
return 0;
return sp->read(sp, SPI_GCORES_RX(idx));
return sp->read(sp, SPI_OCORES_RX(idx));
}
/**
......@@ -178,7 +180,7 @@ static uint32_t spi_gcores_rx_get(struct spi_gcores *sp, unsigned int idx)
*
* Return: number of bits_per_word
*/
static uint8_t spi_gcores_hw_xfer_bits_per_word(struct spi_gcores *sp)
static uint8_t spi_ocores_hw_xfer_bits_per_word(struct spi_ocores *sp)
{
uint8_t nbits;
......@@ -189,37 +191,37 @@ static uint8_t spi_gcores_hw_xfer_bits_per_word(struct spi_gcores *sp)
return nbits;
}
static void spi_gcores_hw_xfer_tx_push8(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push8(struct spi_ocores *sp)
{
uint32_t data;
data = *((uint8_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 1;
spi_gcores_tx_set(sp, 0, data);
spi_ocores_tx_set(sp, 0, data);
sp->cur_tx_len -= 1;
}
static void spi_gcores_hw_xfer_tx_push16(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push16(struct spi_ocores *sp)
{
uint32_t data;
data = *((uint16_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 2;
spi_gcores_tx_set(sp, 0, data);
spi_ocores_tx_set(sp, 0, data);
sp->cur_tx_len -= 2;
}
static void spi_gcores_hw_xfer_tx_push32(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push32(struct spi_ocores *sp)
{
uint32_t data;
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_gcores_tx_set(sp, 0, data);
spi_ocores_tx_set(sp, 0, data);
sp->cur_tx_len -= 4;
}
static void spi_gcores_hw_xfer_tx_push64(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push64(struct spi_ocores *sp)
{
int i;
......@@ -228,12 +230,12 @@ static void spi_gcores_hw_xfer_tx_push64(struct spi_gcores *sp)
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_gcores_tx_set(sp, i, data);
spi_ocores_tx_set(sp, i, data);
sp->cur_tx_len -= 4;
}
}
static void spi_gcores_hw_xfer_tx_push128(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push128(struct spi_ocores *sp)
{
int i;
......@@ -242,63 +244,63 @@ static void spi_gcores_hw_xfer_tx_push128(struct spi_gcores *sp)
data = *((uint32_t *)sp->cur_tx_buf);
sp->cur_tx_buf += 4;
spi_gcores_tx_set(sp, i, data);
spi_ocores_tx_set(sp, i, data);
sp->cur_tx_len -= 4;
}
}
static void spi_gcores_hw_xfer_rx_push8(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_push8(struct spi_ocores *sp)
{
uint32_t data;
data = spi_gcores_rx_get(sp, 0) & 0x000000FF;
data = spi_ocores_rx_get(sp, 0) & 0x000000FF;
*((uint8_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 1;
sp->cur_rx_len -= 1;
}
static void spi_gcores_hw_xfer_rx_push16(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_push16(struct spi_ocores *sp)
{
uint32_t data;
data = spi_gcores_rx_get(sp, 0) & 0x0000FFFF;
data = spi_ocores_rx_get(sp, 0) & 0x0000FFFF;
*((uint16_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 2;
sp->cur_rx_len -= 2;
}
static void spi_gcores_hw_xfer_rx_push32(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_push32(struct spi_ocores *sp)
{
uint32_t data;
data = spi_gcores_rx_get(sp, 0) & 0xFFFFFFFF;
data = spi_ocores_rx_get(sp, 0) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
sp->cur_rx_len -= 4;
}
static void spi_gcores_hw_xfer_rx_push64(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_push64(struct spi_ocores *sp)
{
int i;
for (i = 0; i < 2; ++i) {
uint32_t data;
data = spi_gcores_rx_get(sp, i) & 0xFFFFFFFF;
data = spi_ocores_rx_get(sp, i) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
sp->cur_rx_len -= 4;
}
}
static void spi_gcores_hw_xfer_rx_push128(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_push128(struct spi_ocores *sp)
{
int i;
for (i = 0; i < 4; ++i) {
uint32_t data;
data = spi_gcores_rx_get(sp, i) & 0xFFFFFFFF;
data = spi_ocores_rx_get(sp, i) & 0xFFFFFFFF;
*((uint32_t *)sp->cur_rx_buf) = data;
sp->cur_rx_buf += 4;
sp->cur_rx_len -= 4;
......@@ -309,21 +311,21 @@ static void spi_gcores_hw_xfer_rx_push128(struct spi_gcores *sp)
* Write pending data in RX registers
* @sp: SPI OCORE controller
*/
static void spi_gcores_hw_xfer_tx_push(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_tx_push(struct spi_ocores *sp)
{
uint8_t nbits;
nbits = spi_gcores_hw_xfer_bits_per_word(sp);
nbits = spi_ocores_hw_xfer_bits_per_word(sp);
if (nbits >= 8) {
spi_gcores_hw_xfer_tx_push8(sp);
spi_ocores_hw_xfer_tx_push8(sp);
} else if (nbits >= 16) {
spi_gcores_hw_xfer_tx_push16(sp);
spi_ocores_hw_xfer_tx_push16(sp);
} else if (nbits >= 32) {
spi_gcores_hw_xfer_tx_push32(sp);
spi_ocores_hw_xfer_tx_push32(sp);
} else if (nbits >= 64) {
spi_gcores_hw_xfer_tx_push64(sp);
spi_ocores_hw_xfer_tx_push64(sp);
} else if (nbits >= 128) {
spi_gcores_hw_xfer_tx_push128(sp);
spi_ocores_hw_xfer_tx_push128(sp);
}
}
......@@ -331,34 +333,34 @@ static void spi_gcores_hw_xfer_tx_push(struct spi_gcores *sp)
* Read received data from TX registers
* @sp: SPI OCORE controller
*/
static void spi_gcores_hw_xfer_rx_pop(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_rx_pop(struct spi_ocores *sp)
{
uint8_t nbits;
nbits = spi_gcores_hw_xfer_bits_per_word(sp);
nbits = spi_ocores_hw_xfer_bits_per_word(sp);
if (nbits >= 8) {
spi_gcores_hw_xfer_rx_push8(sp);
spi_ocores_hw_xfer_rx_push8(sp);
} else if (nbits >= 16) {
spi_gcores_hw_xfer_rx_push16(sp);
spi_ocores_hw_xfer_rx_push16(sp);
} else if (nbits >= 32) {
spi_gcores_hw_xfer_rx_push32(sp);
spi_ocores_hw_xfer_rx_push32(sp);
} else if (nbits >= 64) {
spi_gcores_hw_xfer_rx_push64(sp);
spi_ocores_hw_xfer_rx_push64(sp);
} else if (nbits >= 128) {
spi_gcores_hw_xfer_rx_push128(sp);
spi_ocores_hw_xfer_rx_push128(sp);
}
}
static void spi_gcores_hw_xfer_start(struct spi_gcores *sp)
static void spi_ocores_hw_xfer_start(struct spi_ocores *sp)
{
unsigned int cs = sp->master->cur_msg->spi->chip_select;
/* Optimize:
* Probably we can avoid to write CTRL DIVIDER and CS everytime
*/
spi_gcores_hw_xfer_config(sp, sp->cur_ctrl, sp->cur_divider);
spi_gcores_hw_xfer_cs(sp, cs, 1);
spi_gcores_hw_xfer_go(sp);
spi_ocores_hw_xfer_config(sp, sp->cur_ctrl, sp->cur_divider);
spi_ocores_hw_xfer_cs(sp, cs, 1);
spi_ocores_hw_xfer_go(sp);
}
/**
......@@ -374,7 +376,7 @@ static void spi_gcores_hw_xfer_start(struct spi_gcores *sp)
*
* Return: 0 on success, -ETIMEDOUT on timeout
*/
static int spi_gcores_wait(struct spi_gcores *sp,
static int spi_ocores_wait(struct spi_ocores *sp,
int reg, uint32_t mask, uint32_t val,
const unsigned long timeout)
{
......@@ -400,11 +402,11 @@ static int spi_gcores_wait(struct spi_gcores *sp,
*
* return: 0 on success, -ETIMEDOUT on timeout
*/
static int spi_gcores_hw_xfer_wait_complete(struct spi_gcores *sp,
static int spi_ocores_hw_xfer_wait_complete(struct spi_ocores *sp,
const unsigned long timeout)
{
return spi_gcores_wait(sp, SPI_GCORES_CTRL,
SPI_GCORES_CTRL_BUSY, 0, timeout);
return spi_ocores_wait(sp, SPI_OCORES_CTRL,
SPI_OCORES_CTRL_BUSY, 0, timeout);
}
/**
......@@ -414,7 +416,7 @@ static int spi_gcores_hw_xfer_wait_complete(struct spi_gcores *sp,
*
* Return: 0 on success, otherwise a negative errno
*/
static int spi_gcores_sw_xfer_finish(struct spi_gcores *sp)
static int spi_ocores_sw_xfer_finish(struct spi_ocores *sp)
{
if (sp->cur_xfer->delay_usecs)
udelay(sp->cur_xfer->delay_usecs);
......@@ -422,10 +424,10 @@ static int spi_gcores_sw_xfer_finish(struct spi_gcores *sp)
unsigned int cs;
cs = sp->master->cur_msg->spi->chip_select;
spi_gcores_hw_xfer_cs(sp, cs, 0);
spi_ocores_hw_xfer_cs(sp, cs, 0);
}
spi_gcores_hw_xfer_config(sp, 0, 0);
spi_ocores_hw_xfer_config(sp, 0, 0);
sp->cur_xfer = NULL;
sp->cur_tx_buf = NULL;
......@@ -444,12 +446,12 @@ static int spi_gcores_sw_xfer_finish(struct spi_gcores *sp)
* -ENODATA when there are no transfers left,
* -EINVAL invalid bit per word
*/
static int spi_gcores_sw_xfer_next_init(struct spi_gcores *sp)
static int spi_ocores_sw_xfer_next_init(struct spi_ocores *sp)
{
struct list_head *head = &sp->master->cur_msg->transfers;
uint32_t hz;
if (spi_gcores_hw_xfer_bits_per_word(sp) > 128)
if (spi_ocores_hw_xfer_bits_per_word(sp) > 128)
return -EINVAL;
if (!sp->cur_xfer) {
......@@ -466,7 +468,7 @@ static int spi_gcores_sw_xfer_next_init(struct spi_gcores *sp)
}
sp->cur_ctrl = sp->ctrl_base;
sp->cur_ctrl |= spi_gcores_hw_xfer_bits_per_word(sp);
sp->cur_ctrl |= spi_ocores_hw_xfer_bits_per_word(sp);
if (sp->cur_xfer->speed_hz)
hz = sp->cur_xfer->speed_hz;
else
......@@ -486,17 +488,17 @@ static int spi_gcores_sw_xfer_next_init(struct spi_gcores *sp)
*
* Return: 0 on success, -ENODEV when missing transfers
*/
static int spi_gcores_sw_xfer_next_start(struct spi_gcores *sp)
static int spi_ocores_sw_xfer_next_start(struct spi_ocores *sp)
{
int err;
err = spi_gcores_sw_xfer_next_init(sp);
err = spi_ocores_sw_xfer_next_init(sp);
if (err) {
spi_finalize_current_message(sp->master);
return err;
}
spi_gcores_hw_xfer_tx_push(sp);
spi_gcores_hw_xfer_start(sp);
spi_ocores_hw_xfer_tx_push(sp);
spi_ocores_hw_xfer_start(sp);
return 0;
}
......@@ -506,7 +508,7 @@ static int spi_gcores_sw_xfer_next_start(struct spi_gcores *sp)
* @sp: SPI OCORE controller
* Return: True is there are still pending data in the current transfer
*/
static bool spi_gcores_sw_xfer_tx_pending(struct spi_gcores *sp)
static bool spi_ocores_sw_xfer_tx_pending(struct spi_ocores *sp)
{
return sp->cur_tx_len;
}
......@@ -517,20 +519,20 @@ static bool spi_gcores_sw_xfer_tx_pending(struct spi_gcores *sp)
*
* Return: 0 on success, -ENODATA when there is nothing to process
*/
static int spi_gcores_process(struct spi_gcores *sp)
static int spi_ocores_process(struct spi_ocores *sp)
{
uint32_t ctrl = sp->read(sp, SPI_GCORES_CTRL);
uint32_t ctrl = sp->read(sp, SPI_OCORES_CTRL);
if (ctrl & SPI_GCORES_CTRL_BUSY)
if (ctrl & SPI_OCORES_CTRL_BUSY)
return -ENODATA;
spi_gcores_hw_xfer_rx_pop(sp);
if (spi_gcores_sw_xfer_tx_pending(sp)) {
spi_gcores_hw_xfer_tx_push(sp);
spi_gcores_hw_xfer_start(sp);
spi_ocores_hw_xfer_rx_pop(sp);
if (spi_ocores_sw_xfer_tx_pending(sp)) {
spi_ocores_hw_xfer_tx_push(sp);
spi_ocores_hw_xfer_start(sp);
} else {
spi_gcores_sw_xfer_finish(sp);
spi_gcores_sw_xfer_next_start(sp);
spi_ocores_sw_xfer_finish(sp);
spi_ocores_sw_xfer_next_start(sp);
}
return 0;
......@@ -544,25 +546,25 @@ static int spi_gcores_process(struct spi_gcores *sp)
* Return: 0 on success, -ENODATA when there is nothing to process, -ETIMEDOUT
* when is still pending after timeout
*/
static int spi_gcores_process_poll(struct spi_gcores *sp, unsigned int timeout)
static int spi_ocores_process_poll(struct spi_ocores *sp, unsigned int timeout)
{
int err;
err = spi_gcores_hw_xfer_wait_complete(sp, msecs_to_jiffies(timeout));
err = spi_ocores_hw_xfer_wait_complete(sp, msecs_to_jiffies(timeout));
if (err)
return err;
err = spi_gcores_process(sp);
err = spi_ocores_process(sp);
if (err)
return err;
return 0;
}
static irqreturn_t spi_gcores_irq_handler(int irq, void *arg)
static irqreturn_t spi_ocores_irq_handler(int irq, void *arg)
{
struct spi_gcores *sp = arg;
struct spi_ocores *sp = arg;
int err;
err = spi_gcores_process(sp);
err = spi_ocores_process(sp);
if (err)
return IRQ_NONE;
......@@ -572,31 +574,32 @@ static irqreturn_t spi_gcores_irq_handler(int irq, void *arg)
/**
* Transfer one SPI message
*/
static int spi_gcores_transfer_one_message(struct spi_master *master,
static int spi_ocores_transfer_one_message(struct spi_master *master,
struct spi_message *mesg)
{
struct spi_gcores *sp = spi_master_get_devdata(master);
struct spi_ocores *sp = spi_master_get_devdata(master);
int err = 0;
err = spi_gcores_sw_xfer_next_start(sp);
if (sp->flags & SPI_GCORES_FLAG_POLL) {
err = spi_ocores_sw_xfer_next_start(sp);
if (sp->flags & SPI_OCORES_FLAG_POLL) {
do {
err =spi_gcores_process_poll(sp, 100);
err =spi_ocores_process_poll(sp, 100);
} while (!err);
}
return 0;
}
static int spi_gcores_probe(struct platform_device *pdev)
static int spi_ocores_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct spi_gcores *sp;
struct spi_gcores_platform_data *pdata;
struct spi_ocores *sp;
struct spi_ocores_platform_data *pdata;
struct resource *r;
int err;
int irq;
pr_info("%s:%d\n", __func__, __LINE__);
master = spi_alloc_master(&pdev->dev, sizeof(*sp));
if (!master) {
dev_err(&pdev->dev, "failed to allocate spi master\n");
......@@ -616,17 +619,17 @@ static int spi_gcores_probe(struct platform_device *pdev)
sp->clock_hz = pdata->clock_hz;
/* configure SPI master */
master->setup = spi_gcores_setup;
master->cleanup = spi_gcores_cleanup;
master->transfer_one_message = spi_gcores_transfer_one_message;
master->num_chipselect = pdata->num_chipselect;
master->setup = spi_ocores_setup;
master->cleanup = spi_ocores_cleanup;
master->transfer_one_message = spi_ocores_transfer_one_message;
master->num_chipselect = SPI_OCORES_CS_MAX_N;
master->bits_per_word_mask = BIT(32 - 1);
if (pdata->big_endian) {
sp->read = spi_gcores_ioread32be;
sp->write = spi_gcores_iowrite32be;
sp->read = spi_ocores_ioread32be;
sp->write = spi_ocores_iowrite32be;
} else {
sp->read = spi_gcores_ioread32;
sp->write = spi_gcores_iowrite32;
sp->read = spi_ocores_ioread32;
sp->write = spi_ocores_iowrite32;
}
/* assign resources */
......@@ -639,7 +642,7 @@ static int spi_gcores_probe(struct platform_device *pdev)
irq = platform_get_irq(pdev, 0);
if (irq == -ENXIO) {
sp->flags |= SPI_GCORES_FLAG_POLL;
sp->flags |= SPI_OCORES_FLAG_POLL;
} else {
if (irq < 0) {
err = irq;
......@@ -647,9 +650,9 @@ static int spi_gcores_probe(struct platform_device *pdev)
}
}
if (!(sp->flags & SPI_GCORES_FLAG_POLL)) {
sp->ctrl_base |= SPI_GCORES_CTRL_IE;
err = request_any_context_irq(irq, spi_gcores_irq_handler,
if (!(sp->flags & SPI_OCORES_FLAG_POLL)) {
sp->ctrl_base |= SPI_OCORES_CTRL_IE;
err = request_any_context_irq(irq, spi_ocores_irq_handler,
0, pdev->name, sp);
if (err < 0) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
......@@ -664,20 +667,23 @@ static int spi_gcores_probe(struct platform_device *pdev)
return 0;
err_reg_spi:
if (!(sp->flags & SPI_GCORES_FLAG_POLL))
pr_info("%s:%d\n", __func__, __LINE__);
if (!(sp->flags & SPI_OCORES_FLAG_POLL))
free_irq(irq, sp);
err_irq:
err_get_irq:
pr_info("%s:%d\n", __func__, __LINE__);
devm_iounmap(&pdev->dev, sp->mem);
err_get_mem:
err_get_pdata:
pr_info("%s:%d\n", __func__, __LINE__);
spi_master_put(master);
return err;
}
static int spi_gcores_remove(struct platform_device *pdev)
static int spi_ocores_remove(struct platform_device *pdev)
{
struct spi_gcores *sp = platform_get_drvdata(pdev);
struct spi_ocores *sp = platform_get_drvdata(pdev);
int irq = platform_get_irq(pdev, 0);
if (irq > 0)
......@@ -690,27 +696,31 @@ static int spi_gcores_remove(struct platform_device *pdev)
return 0;
}
static const struct platform_device_id spi_gcores_id_table[] = {
static const struct platform_device_id spi_ocores_id_table[] = {
{
.name = "ocores-spi",
.driver_data = TYPE_OCORES,
},
{
.name = "ocores-i2c",
.driver_data = TYPE_GCORES,
.name = "spi-ocores",
.driver_data = TYPE_OCORES,
},
{ .name = "" }, /* last */
};
static struct platform_driver spi_gcores_driver = {
.probe = spi_gcores_probe,
.remove = spi_gcores_remove,
static struct platform_driver spi_ocores_driver = {
.probe = spi_ocores_probe,
.remove = spi_ocores_remove,
.driver = {
.name = "spi-gcores",
.name = "ocores-spi",
.owner = THIS_MODULE,
},
.id_table = spi_gcores_id_table,
.id_table = spi_ocores_id_table,
};
module_platform_driver(spi_gcores_driver);
module_platform_driver(spi_ocores_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_DESCRIPTION("SPI controller driver for OHWR General-Cores SPI Master");
MODULE_LICENSE("GPL");
MODULE_VERSION(VERSION);
MODULE_DEVICE_TABLE(platform, spi_gcores_id_table);
MODULE_DEVICE_TABLE(platform, spi_ocores_id_table);
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