... | @@ -8,30 +8,139 @@ Files used for the |
... | @@ -8,30 +8,139 @@ Files used for the |
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review:
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review:
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https://www.ohwr.org/project/spec/tree/15/trunk/circuit_board/SimplePCIeFMCCarrier/PCB-Layout
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https://www.ohwr.org/project/spec/tree/15/trunk/circuit_board/SimplePCIeFMCCarrier/PCB-Layout
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The following is a compilation of the e-mail exchanges of the review.
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- there shouldn't be any power/ground plane on the PCIe tongue (remove
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- there shouldn't be any power/ground plane on the PCIe tongue (remove
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the copper from under the contacts)
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the copper from under the contacts)
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<!-- end list -->
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- clk0\_m2c\_p/n - it should be a global clock line
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- clk0\_m2c\_p/n - it should be a global clock line
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- *you wrote recently:* "m2c\_clkx and can be connected to any
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other bank. "
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- *I can connect it to bank0.*
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<!-- end list -->
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- make sure there's a solder mask over all vias
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- make sure there's a solder mask over all vias
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*This I missed during last corrections, before I applied it to all
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of them.*
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<!-- end list -->
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- LA17\_CC, LA18\_CC should be connected to a global clock
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- LA17\_CC, LA18\_CC should be connected to a global clock
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- *I have to check it, didn't you told last time about LA16 and
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LA17?*
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- resistance divider for GCLK16/17 (pseudo-differential input for
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- resistance divider for GCLK16/17 (pseudo-differential input for
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CLK25\_VCXO)
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CLK25\_VCXO)
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- *Ok, there is already 22R resistor, but I will add real
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divider.*
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- Pablo: *This is to divide the 3V3 and connect it as a VREF
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to the unused GCLK16/17 (I do not have the schematic on my
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eyes sorry) . The excursion on the IVT oscillator can
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sometimes be very low (only 0.8V), so I think in case we
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ever mount this option it is better to use it as pseudo
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LVDS.*
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- single ground plane (no cuts)
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- single ground plane (no cuts)
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- Grzeg: *I know exactly why I added the cut. It is to limit
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current propagation around the board. The input and coil AC
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current caused by switching should enclose as close as possible
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to the DC/DC converter. The cuts make sure that these current
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loops are local and do not propagate around the PCB. I saw this
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idea in many reference designs i.e. 4-layer main boards.*
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- Erik: *We didn't feel very strongly about this, but we liked
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to remove it anyway. But as I'd like to have the board as
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simple as possible and use tricks only when really needed,
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*please remove these cuts and have a solid ground plane*. I
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take the responsibility if it doesn't work because of
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that.*
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*Reasoning:*
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- *Simpler gives less troubles in most cases. So only make
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more complicated when absolutely needed.*
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- *The design will be easier to understand (useful for
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open designs).*
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- \_our direct experience: the fast ADC FMC board has a
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DC/DC and uses solid ground planes and has an excellent
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good SNR. This also has been verified with an analog
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specialist**. And this all on a very dense and small
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card. The SPEC is digital so should have no problems at
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all.\_**: "I think that just having a good solid GND
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plane everywhere will give best results overall (or
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maybe 2 GND planes if you have enough PCB layers)."
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- remove the 1.00 mm dimension from L5
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- remove the 1.00 mm dimension from L5
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- *OK*
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- you can reverse polarities for PER pairs
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- you can reverse polarities for PER pairs
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- *OK*
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- cleanup (acute angle trace - pad connections in few places)
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- cleanup (acute angle trace - pad connections in few places)
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- *in case of coils I did it on purpose*
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- remove EDA number from the silkscreen
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- remove EDA number from the silkscreen
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- *OK*
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<!-- end list -->
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- remove "Cagebot" , "CageTop" from the SFP
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- remove "Cagebot" , "CageTop" from the SFP
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- *OK*
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- put CERN logo somewhere and a big name "SPEC"
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- put CERN logo somewhere and a big name "SPEC"
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- *OK*
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- put boxes with layer numbers on the PCB area
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- put boxes with layer numbers on the PCB area
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- *OK*
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- put "JTAG" text next to JTAG connector
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- put "JTAG" text next to JTAG connector
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- *OK*
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- clk1\_m2c\_p/n should be connected to a gclk too. Suggest to use
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- clk1\_m2c\_p/n should be connected to a gclk too. Suggest to use
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Bank 1.
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Bank 1.
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- The lines on Layer 3 and Layer 4 sometimes are precisely above each
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other. Yes we know, there is 1mm distance, but as it is prepreg it
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is not precise. Furthermore there is enough space on each layer, so
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can you please tear them somewhat apart so that they are not above
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each other anymore?
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- *OK*
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<!-- end list -->
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- PCIe spec: total thickness 1.57 +/- 0.06 mm. The board actually is
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1.47mm. Can you make that it becomes 1.57?
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- *OK*
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- Add the LHC name "CFCKA"
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- *may be wrong actually*
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Erik van der Bij - 8 October 2010
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Erik van der Bij - 8 October 2010
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