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# Review05102010
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## PCB layout review held on 5 October 2010
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Present: P. Alvarez Sanchez, M. Cattin, T. Wlostowski, E.van der Bij
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Files used for the
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review:
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https://www.ohwr.org/project/spec/tree/15/trunk/circuit_board/SimplePCIeFMCCarrier/PCB-Layout
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-----
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- there shouldn't be any power/ground plane on the PCIe tongue (remove
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the copper from under the contacts)
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- clk0\_m2c\_p/n - it should be a global clock line
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- make sure there's a solder mask over all vias
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- LA17\_CC, LA18\_CC should be connected to a global clock
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- resistance divider for GCLK16/17 (pseudo-differential input for
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CLK25\_VCXO)
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- single ground plane (no cuts)
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- remove the 1.00 mm dimension from L5
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- you can reverse polarities for PER pairs
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- cleanup (acute angle trace - pad connections in few places)
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- remove EDA number from the silkscreen
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- remove "Cagebot" , "CageTop" from the SFP
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- put CERN logo somewhere and a big name "SPEC"
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- put boxes with layer numbers on the PCB area
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- put "JTAG" text next to JTAG connector
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<!-- end list -->
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- clk1\_m2c\_p/n should be connected to a gclk too. Suggest to use
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Bank 1.
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-----
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Erik van der Bij - 8 October 2010
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