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# Simple PCIe FMC carrier (SPEC)
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## Project description
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The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
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SFP connector. On the PCIe side it has a 4-lane interface, while the FMC
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mezzanine slot uses a low-pin count connector. This board is optimised
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for cost and will be usable with most of the FMC cards designed within
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the OHR project (e.g. ADC cards, Fine Delay). For boards needing more
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possibilities (e.g. programmable clock resources, fast SRAM, fast
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interconnect between carriers), the [FMC PCIe
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Carrier](https://www.ohwr.org/project/fmc-pci-carrier) or its [VME
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counter part](https://www.ohwr.org/project/fmc-vme-carrier) can be used.
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Other FMC projects and the FMC standard are described in [FMC
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Projects](https://www.ohwr.org/project/fmc-projects).
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## Main Features
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\* 4-lane PCIe (Gennum GN4124)
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\* FMC slot with low pin count (LPC) connector
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o Vadj fixed to 2.5V
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o No dedicated clock signals from Carrier to FMC (only available on HPC
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pins)
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o LPC cheaper than HPC and also easier to mount
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o FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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\* 1 Spartan6 FPGA (XC6SLX45T)
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\* Simple clocking resources
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o 25 MHz oscillator
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o TCXO controlled by a DAC
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\* On board memory
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o A 2Gbit DDR3
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o 1 SPI 128Mbit flash PROM for multiboot FPGA powerup configuration,
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storage of the FPGA firmware or of critical data
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\* Front panel containing
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o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
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([WhiteRabbit](https://www.ohwr.org/project/white-rabbit) support)
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o Programmable LED
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o FMC front panel
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\* Internal connectors
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o 1 JTAG header for Xilinx programming during debugging
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o 1 or 2 SATA connectors if don't add much cost
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\* FPGA configuration. The FPGA can optionally be programmed from:
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o GN4124 SPRIO interface (loaded by software driver at startup)
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o JTAG header
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o SPI 128Mbit flash PROM
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o selectable by assembly of 0 Ohm resistors. Default option would be
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loading via the GN4124 at driver startup.
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\* Optimised for cost
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-----
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## Detailed project information
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>22-06-2010</td>
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<td>Start of project. Design will be done by an external company, based on the <a href="https://www.ohwr.org/project/fmc-pci-carrier">FMC PCIe Carrier</a>. Reviewing will be done by CERN.</td>
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</tr>
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<tr class="odd">
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<td>29-06-2010</td>
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<td>Main features reviewed by JS, PA, MC & EB. Design can start.</td>
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</tr>
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<tr class="even">
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<td>12-07-2010</td>
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<td>First schematics published. Ready for review.</td>
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</tr>
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<tr class="odd">
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<td>16-07-2010</td>
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<td>First review held. Considered as a preliminary review as schematics not finished.</td>
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</tr>
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<tr class="even">
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<td>24-07-2010</td>
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<td>Second version schematics published.</td>
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</tr>
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<tr class="odd">
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<td>03-08-2010</td>
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<td>Second schematics review held. FMC to Xilinx bank connections not correct. Clock missing. Supply Xilinx wrong. Cleanup required.</td>
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</tr>
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<tr class="even">
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<td>03-09-2010</td>
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<td>Schematics corrected. Waiting for a final schematics review from CERN.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij - 3 September 2010
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### Files
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* [spec.JPG](/uploads/b9ea47be8f4a6a411dd444e432868bd7/spec.JPG)
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* [spec_v2.jpg](/uploads/1da041f7ed1da9b42d1b83f77528a11d/spec_v2.jpg)
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* [spec_v1.1_top.JPG](/uploads/23a127884e2820d707e58c6119cde69d/spec_v1.1_top.JPG)
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* [spec_v1.1_bottom.JPG](/uploads/2240e46a37d3fab76b4e4953ebcc7e9a/spec_v1.1_bottom.JPG)
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* [SPEC_top_high_res.jpg](/uploads/036da7721683445ec3e5d5d0a8a855c8/SPEC_top_high_res.jpg)
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* [SPEC_bottom_high_res.jpg](/uploads/0e72fd9272d29cd6e0e67de39924cb78/SPEC_bottom_high_res.jpg) |
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