... | ... | @@ -220,12 +220,16 @@ Clock missing. Supply Xilinx wrong. Cleanup required.</td> |
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<td>16-05-2011</td>
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<td>Schematics, layout and production documents for V2 are available in [EDMS](https://edms.cern.ch/nav/P:EDA-02189:V0/I:EDA-02189-V2-0:V0/TAB4)</td>
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</tr>
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<tr class="even">
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<td>20-05-2011</td>
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<td>CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 16 May 2011
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 20 May 2011
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... | ... | |