... | ... | @@ -180,12 +180,20 @@ Clock missing. Supply Xilinx wrong. Cleanup required.</td> |
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<td>06-02-2011</td>
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<td>Packet transmission and reception works!</td>
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</tr>
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<tr class="even">
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<td>24-02-2011</td>
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<td>All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.</td>
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</tr>
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<tr class="odd">
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<td>01-03-2011</td>
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<td>Planned review of "V1.1" for fast production for WR developers.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij, Tomasz Wlostowski - 22 February 2011
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Erik van der Bij, Tomasz Wlostowski - 24 February 2011
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... | ... | |