... | @@ -27,8 +27,9 @@ o FMC connectivity: all 34 differential pairs connected, 1 GTP |
... | @@ -27,8 +27,9 @@ o FMC connectivity: all 34 differential pairs connected, 1 GTP |
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transceiver with clock, 2 clock pairs, JTAG
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transceiver with clock, 2 clock pairs, JTAG
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\* 1 Spartan6 FPGA (XC6SLX45T)
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\* 1 Spartan6 FPGA (XC6SLX45T)
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\* Simple clocking resources
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\* Simple clocking resources
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o 25 MHz oscillator
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o 1 10-280 MHz Programmable XO Oscillator (Silicon Labs Si570)
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o TCXO controlled by a DAC
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o 2 25 MHz TCXOs controlled by a DAC
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o 1 low-jitter frequency synthesizer (TI CDCM61004)
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\* On board memory
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\* On board memory
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o A 2Gbit DDR3
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o A 2Gbit DDR3
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o 1 SPI 128Mbit flash PROM for multiboot FPGA powerup configuration,
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o 1 SPI 128Mbit flash PROM for multiboot FPGA powerup configuration,
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... | @@ -91,12 +92,16 @@ loading via the GN4124 at driver startup. |
... | @@ -91,12 +92,16 @@ loading via the GN4124 at driver startup. |
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<td>03-09-2010</td>
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<td>03-09-2010</td>
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<td>Schematics corrected. Waiting for a final schematics review from CERN.</td>
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<td>Schematics corrected. Waiting for a final schematics review from CERN.</td>
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</tr>
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</tr>
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<tr class="odd">
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<td>07-09-2010</td>
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<td>Third schematics review held. [review07092010](review07092010)</td>
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|
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</tr>
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</tbody>
|
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</tbody>
|
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</table>
|
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</table>
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|
|
|
-----
|
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-----
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Erik van der Bij - 3 September 2010
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Erik van der Bij - 8 September 2010
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... | | ... | |