... | ... | @@ -171,6 +171,10 @@ Clock missing. Supply Xilinx wrong. Cleanup required.</td> |
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<td>04-02-2011</td>
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<td>First DDR3 access</td>
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</tr>
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<tr class="even">
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<td>04-02-2011</td>
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<td>WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress...</td>
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</tr>
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</tbody>
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</table>
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... | ... | |