... | ... | @@ -154,7 +154,7 @@ Clock missing. Supply Xilinx wrong. Cleanup required.</td> |
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>05-11-2010</td>
|
|
|
<td>Design finished. <a href="https://edh.cern.ch/Document/SupplyChain/DAI/4476636">Order placed</a> for production of three boards. Expect boards by <del>mid December</del> January.</td>
|
|
|
<td>Design finished. Expect ordered boards by <del>mid December</del> January.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>20-12-2010</td>
|
... | ... | |