... | ... | @@ -2,239 +2,70 @@ |
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>22-06-2010</td>
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<td>Start of project. Design will be done by an external company, based on the <a href="https://www.ohwr.org/project/fmc-pci-carrier">FMC PCIe Carrier</a>.<br />
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Reviewing will be done by CERN.</td>
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</tr>
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<tr class="odd">
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<td>29-06-2010</td>
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<td>Main features reviewed by JS, PA, MC & EB. Design can start.</td>
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</tr>
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<tr class="even">
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<td>12-07-2010</td>
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<td>First schematics published. Ready for review.</td>
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</tr>
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<tr class="odd">
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<td>16-07-2010</td>
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<td>First review held. Considered as a preliminary review as schematics not finished.</td>
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</tr>
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<tr class="even">
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<td>24-07-2010</td>
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<td>Second version schematics published.</td>
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</tr>
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<tr class="odd">
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<td>03-08-2010</td>
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<td>Second schematics review held. FMC to Xilinx bank connections not correct.<br />
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Clock missing. Supply Xilinx wrong. Cleanup required.</td>
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</tr>
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<tr class="even">
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<td>03-09-2010</td>
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<td>Schematics corrected. Waiting for a final schematics review from CERN.</td>
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</tr>
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<tr class="odd">
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<td>07-09-2010</td>
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<td>Third schematics review held. [review07092010](review07092010)</td>
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</tr>
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<tr class="even">
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<td>10-09-2010</td>
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<td>Review comments integrated <a href="review07092010comments" class="uri">review07092010comments</a>. Start of PCB layout.</td>
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</tr>
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<tr class="odd">
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<td>21-09-2010</td>
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<td>PCB layout being made. Will fit on a 6-layer board.</td>
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</tr>
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<tr class="even">
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<td>27-09-2010</td>
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<td>PCB layout 'ready'.</td>
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</tr>
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<tr class="odd">
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<td>01-10-2010</td>
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<td>PCB layout modified before review.</td>
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</tr>
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<tr class="even">
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<td>04-10-2010</td>
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<td>Preliminary PCB layout review requiring modifications to layout. [review04102010](review04102010)</td>
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</tr>
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<tr class="odd">
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<td>05-10-2010</td>
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<td>PCB layout review held. [review05102010](review05102010)</td>
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</tr>
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<tr class="even">
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<td>08-10-2010</td>
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<td><a href="https://edh.cern.ch/Document/SupplyChain/DAI/4476636">Order</a> placed for production of three prototypes.</td>
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</tr>
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<tr class="odd">
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<td>18-10-2010</td>
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<td>Some final mods to the schematics and PCB. Design passses CERN's design office for standard production files.</td>
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</tr>
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<tr class="even">
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<td>19-10-2010</td>
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<td>Board could not generate interrupts. Found before finalising production files.</td>
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</tr>
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<tr class="odd">
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<td>20-10-2010</td>
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<td>Vias designed next to BGA pads which may cause production problems. Needs rework of layout.</td>
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</tr>
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<tr class="even">
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<td>29-10-2010</td>
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<td>Received improved layout. Will pass via CERN's design office.</td>
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</tr>
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<tr class="odd">
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<td>05-11-2010</td>
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<td>Design finished. Expect ordered boards by <del>mid December</del> January.</td>
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</tr>
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<tr class="even">
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<td>20-12-2010</td>
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<td>Production of 3 prototype board finished (see photo above)</td>
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</tr>
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<tr class="odd">
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<td>19-01-2011</td>
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<td>Three prototypes arrived at CERN.</td>
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</tr>
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<tr class="even">
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<td>19-01-2011</td>
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<td>Started testing V1 [TestingV1](TestingV1)</td>
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</tr>
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<tr class="odd">
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<td>04-02-2011</td>
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<td>First DDR3 access</td>
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</tr>
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<tr class="even">
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<td>04-02-2011</td>
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<td>WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress...</td>
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</tr>
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<tr class="odd">
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<td>06-02-2011</td>
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<td>Packet transmission and reception works!</td>
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</tr>
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<tr class="even">
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<td>24-02-2011</td>
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<td>All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.</td>
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</tr>
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<tr class="odd">
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<td>02-03-2011</td>
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<td>Review of "V1.1" schematics and PCB.</td>
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</tr>
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<tr class="even">
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<td>07-03-2011</td>
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<td>Ordered 10 "V1.1" boards for CERN. Company will produce extra for <a href="https://www.ohwr.org/project/white-rabbit">WR</a> development.</td>
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</tr>
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<tr class="odd">
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<td>11-04-2011</td>
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<td>Improved version of "V1.1" layout sent for verification by CERN's design office. Planned ready by 29-04-2011.</td>
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</tr>
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<tr class="even">
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<td>18-04-2011</td>
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<td>First V1.1 prototypes received, start testing them.</td>
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</tr>
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<tr class="odd">
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<td>02-05-2011</td>
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<td>V1.1 partly tested. Cleaning up schematics for production. Found missing pull-ups.</td>
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</tr>
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<tr class="even">
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<td>09-05-2011</td>
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<td>Review of updated schematics planned to be held on 11-05-2011. [review11052011](review11052011)</td>
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</tr>
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<tr class="odd">
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<td>16-05-2011</td>
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<td>Schematics, layout and production documents for V2 are available in [EDMS](https://edms.cern.ch/nav/P:EDA-02189:V0/I:EDA-02189-V2-0:V0/TAB4)</td>
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</tr>
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<tr class="even">
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<td>20-05-2011</td>
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<td>CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October.</td>
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</tr>
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<tr class="odd">
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<td>31-05-2011</td>
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<td>Sent order for 3 production prototypes. <a href="http://edh.cern.ch/Info/Order/CA/1519947">Order</a> (CERN only).<br />
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Demo of production test software shown. Needs only minor modifications.</td>
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</tr>
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<tr class="even">
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<td>16-06-2011</td>
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<td>V2 boards being built.</td>
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</tr>
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<tr class="odd">
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<td>01-07-2011</td>
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<td>Three V2 boards received. One fully tested OK. Two only shortly tested.</td>
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</tr>
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<tr class="even">
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<td>14-07-2011</td>
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<td>Modifications for V3 (OHL v1.1, 1 crossover SATA), [changelog](V3ChangeLog)</td>
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</tr>
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<tr class="odd">
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<td>17-07-2011</td>
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<td>Order placed for 70 SPEC cards at Seven Solutions. First batch expected end October.</td>
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</tr>
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<tr class="even">
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<td>25-07-2011</td>
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<td>V3 released. But never built.</td>
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</tr>
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<tr class="odd">
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<td>23-08-2011</td>
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<td>V4 released. Solves a minor mechanical problem with the SFP connector.</td>
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</tr>
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<tr class="even">
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<td>21-11-2011</td>
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<td>Pre-production serie of 10 boards was not compliant to IPC-A-610 (Class 2).</td>
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</tr>
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<tr class="odd">
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<td>16-01-2012</td>
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<td>Will receive <del>8</del> 11 boards by <del>mid February</del> 7 March. (Update 24-02-2012), another 59 by end April.</td>
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</tr>
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<tr class="even">
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<td>14-03-2012</td>
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<td>CERN accepted the 10 preseries boards that were received on 7 March.</td>
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</tr>
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<tr class="odd">
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<td>26-04-2012</td>
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<td>Will receive another 27 cards from Seven Solution by mid-June. And 33 out of the order of 70 later.</td>
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</tr>
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<tr class="even">
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<td>12-06-2012</td>
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<td>SPEC boards passed most restrictive EMC tests for industrial and domestic classes. [Test report](https://www.ohwr.org/project/spec/wikis/Documents/EMC-Test-report).</td>
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</tr>
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<tr class="odd">
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<td>13-06-2012</td>
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<td>CERN ordered 60 cards at INCAA for delivery end September.</td>
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</tr>
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<tr class="even">
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<td>03-07-2012</td>
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<td>Seven Solutions delivered 52 cards. 8 to be delivered later.</td>
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</tr>
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<tr class="odd">
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<td>18-07-2012</td>
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<td>Seven Solutions delivered final 8 cards.</td>
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</tr>
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<tr class="even">
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<td>10-09-2012</td>
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<td>CERN entered the modules in the stock for later use in LHC and other accelerators.</td>
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</tr>
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<tr class="odd">
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<td>30-04-2013</td>
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<td>60 SPEC boards received from INCAA.</td>
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</tr>
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<tr class="even">
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<td>13-06-2012</td>
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<td>Board available from three commercial producers.</td>
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</tr>
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<tr class="odd">
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<td>03-12-2013</td>
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<td>Labview Driver available for <a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/wiki">FMC DEL 1ns 4cha</a> and [FMC TDC 1ns 5cha](https://www.ohwr.org/project/fmc-tdc/wiki).</td>
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</tr>
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<tr class="even">
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<td>02-12-2016</td>
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<td>PCIe bridge component (Gennum GN4124) obsolete and not available anymore. A new card should be designed.</td>
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</tr>
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</tbody>
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</table>
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|**Date**|**Event**|
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|----|----|
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|22-06-2010|Start of project. Design will be done by an external company, based on the [FMC PCIe Carrier](https://www.ohwr.org/project/fmc-pci-carrier).
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Reviewing will be done by CERN.|
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|29-06-2010|Main features reviewed by JS, PA, MC & EB. Design can start.|
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|12-07-2010|First schematics published. Ready for review.|
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|16-07-2010|First review held. Considered as a preliminary review as schematics not finished.|
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|24-07-2010|Second version schematics published.|
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|
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|03-08-2010|Second schematics review held. FMC to Xilinx bank connections not correct.
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|
|
Clock missing. Supply Xilinx wrong. Cleanup required.|
|
|
|
|03-09-2010|Schematics corrected. Waiting for a final schematics review from CERN.|
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|
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|07-09-2010|Third schematics review held. [review07092010](review07092010)|
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|10-09-2010|Review comments integrated [review07092010comments](review07092010comments). Start of PCB layout.|
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|21-09-2010|PCB layout being made. Will fit on a 6-layer board.|
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|27-09-2010|PCB layout 'ready'.|
|
|
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|01-10-2010|PCB layout modified before review.|
|
|
|
|04-10-2010|Preliminary PCB layout review requiring modifications to layout. [review04102010](review04102010)|
|
|
|
|05-10-2010|PCB layout review held. [review05102010](review05102010)|
|
|
|
|08-10-2010|[Order](https://edh.cern.ch/Document/SupplyChain/DAI/4476636) placed for production of three prototypes.|
|
|
|
|18-10-2010|Some final mods to the schematics and PCB. Design passses CERN's design office for standard production files.|
|
|
|
|19-10-2010|Board could not generate interrupts. Found before finalising production files.|
|
|
|
|20-10-2010|Vias designed next to BGA pads which may cause production problems. Needs rework of layout.|
|
|
|
|29-10-2010|Received improved layout. Will pass via CERN's design office.|
|
|
|
|05-11-2010|Design finished. Expect ordered boards by mid December January.|
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|20-12-2010|Production of 3 prototype board finished (see photo above)|
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|19-01-2011|Three prototypes arrived at CERN.|
|
|
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|19-01-2011|Started testing V1 [TestingV1](TestingV1)|
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|04-02-2011|First DDR3 access|
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|
|
|04-02-2011|WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress...|
|
|
|
|06-02-2011|Packet transmission and reception works!|
|
|
|
|24-02-2011|All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.|
|
|
|
|02-03-2011|Review of "V1.1" schematics and PCB.|
|
|
|
|07-03-2011|Ordered 10 "V1.1" boards for CERN. Company will produce extra for [WR](https://www.ohwr.org/project/white-rabbit) development.|
|
|
|
|11-04-2011|Improved version of "V1.1" layout sent for verification by CERN's design office. Planned ready by 29-04-2011.|
|
|
|
|18-04-2011|First V1.1 prototypes received, start testing them.|
|
|
|
|02-05-2011|V1.1 partly tested. Cleaning up schematics for production. Found missing pull-ups.|
|
|
|
|09-05-2011|Review of updated schematics planned to be held on 11-05-2011. [review11052011](review11052011)|
|
|
|
|16-05-2011|Schematics, layout and production documents for V2 are available in [EDMS](https://edms.cern.ch/nav/P:EDA-02189:V0/I:EDA-02189-V2-0:V0/TAB4)|
|
|
|
|20-05-2011|CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October.|
|
|
|
|31-05-2011|Sent order for 3 production prototypes. [Order](http://edh.cern.ch/Info/Order/CA/1519947) (CERN only).
|
|
|
Demo of production test software shown. Needs only minor modifications.|
|
|
|
|16-06-2011|V2 boards being built.|
|
|
|
|01-07-2011|Three V2 boards received. One fully tested OK. Two only shortly tested.|
|
|
|
|14-07-2011|Modifications for V3 (OHL v1.1, 1 crossover SATA), [changelog](V3ChangeLog)|
|
|
|
|17-07-2011|Order placed for 70 SPEC cards at Seven Solutions. First batch expected end October.|
|
|
|
|25-07-2011|V3 released. But never built.|
|
|
|
|23-08-2011|V4 released. Solves a minor mechanical problem with the SFP connector.|
|
|
|
|21-11-2011|Pre-production serie of 10 boards was not compliant to IPC-A-610 (Class 2).|
|
|
|
|16-01-2012|Will receive 8 11 boards by mid February 7 March. (Update 24-02-2012), another 59 by end April.|
|
|
|
|14-03-2012|CERN accepted the 10 preseries boards that were received on 7 March.|
|
|
|
|26-04-2012|Will receive another 27 cards from Seven Solution by mid-June. And 33 out of the order of 70 later.|
|
|
|
|12-06-2012|SPEC boards passed most restrictive EMC tests for industrial and domestic classes. [Test report](https://www.ohwr.org/project/spec/wikis/Documents/EMC-Test-report).|
|
|
|
|13-06-2012|CERN ordered 60 cards at INCAA for delivery end September.|
|
|
|
|03-07-2012|Seven Solutions delivered 52 cards. 8 to be delivered later.|
|
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|
|18-07-2012|Seven Solutions delivered final 8 cards.|
|
|
|
|10-09-2012|CERN entered the modules in the stock for later use in LHC and other accelerators.|
|
|
|
|30-04-2013|60 SPEC boards received from INCAA.|
|
|
|
|13-06-2012|Board available from three commercial producers.|
|
|
|
|03-12-2013|Labview Driver available for [FMC DEL 1ns 4cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wiki) and [FMC TDC 1ns 5cha](https://www.ohwr.org/project/fmc-tdc/wiki).|
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|02-12-2016|PCIe bridge component (Gennum GN4124) obsolete and not available anymore. A new card should be designed.|
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-----
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Erik van der Bij - 14 December 2016
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