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|12-07-2010|First schematics published. Ready for review.|
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|12-07-2010|First schematics published. Ready for review.|
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|16-07-2010|First review held. Considered as a preliminary review as schematics not finished.|
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|16-07-2010|First review held. Considered as a preliminary review as schematics not finished.|
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|24-07-2010|Second version schematics published.|
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|24-07-2010|Second version schematics published.|
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|03-08-2010|Second schematics review held. FMC to Xilinx bank connections not correct.
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|03-08-2010|Second schematics review held. FMC to Xilinx bank connections not correct. <br/>Clock missing. Supply Xilinx wrong. Cleanup required.|
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Clock missing. Supply Xilinx wrong. Cleanup required.|
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|03-09-2010|Schematics corrected. Waiting for a final schematics review from CERN.|
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|03-09-2010|Schematics corrected. Waiting for a final schematics review from CERN.|
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|07-09-2010|Third schematics review held. [review07092010](review07092010)|
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|07-09-2010|Third schematics review held. [review07092010](review07092010)|
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|10-09-2010|Review comments integrated [review07092010comments](review07092010comments). Start of PCB layout.|
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|10-09-2010|Review comments integrated [review07092010comments](review07092010comments). Start of PCB layout.|
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