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# SIS1160 PCI-L I/O add on
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The *sis1160-pci-io* is a front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins of the [SIS1160 FMC carrier](https://www.struck.de/sis1160.html)
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![](/uploads/5c9dc77883dff05bd8cdc352ee220fc2/photo_v2_small.jpg)
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## Functional specifications
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- 5 input/output ports with independently programmable direction (Lemo
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00 connectors).
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- Output levels: LVTTL, capable of driving +2.5 V over a 50-Ohm load.
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At power-up the outputs are in Hi-Z state.
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- Input levels: any logic standard from Vih = 1 V to Vih = 5 V
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(threshold programmable for each input independently).
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- Output Rise/fall times: max. 2 ns.
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- I/O bandwidth: 200 MHz.
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- Programmable 50-Ohm input termination in each channel.
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- LVDS I/O on the carrier side.
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- One of the inputs is capable of driving a global clock net in the
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carrier's FPGA.
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- Inputs and outputs protected against +15V pulses with a pulse width
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of up to 10us @ 50Hz.
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- 4-layer PCB
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- **NOTE:** *This board (up to v2.0) uses EEPROM that is not compatible with VITA 57.1 standard and thus carriers might have difficulties reading configuration from it, see issue #1 and [detailed explanation](https://ohwr.org/project/fmc-projects/wikis/eeprom_24c02).*
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## Block diagram
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![](/uploads/2d0b0f455ea9fd3936c518b4d07a6173/block_diagram.jpg)
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-----
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## Project information
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- Official production documentation: [EDMS
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EDA-02408](https://edms.cern.ch/nav/EDA-02408)
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- [Notes on the hardware design](https://www.ohwr.org/project/fmc-dio-5chttla/wikis/Documents/Note-on-the-DIO-hardware-design)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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- [Users](Users)
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-----
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## Contacts
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### Commercial producers
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- Not commercially available
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### Project
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- [Fernando Hueso González](mailto:Fernando.Hueso@uv.es) - IFIC - Instituto de Física Corpuscular (CSIC/UV), Spain
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-----
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## Project Status
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|**Date**|**Event**|
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|----|----|
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|27-05-2011|Start of project.|
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|19-07-2011|Five cards built. Has some bugs.|
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18 May 2021
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