... | @@ -23,9 +23,10 @@ The SIS1160 carrier board is used together with the [SFMC01](https://www.struck |
... | @@ -23,9 +23,10 @@ The SIS1160 carrier board is used together with the [SFMC01](https://www.struck |
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- Backend:
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- Backend:
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* Board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.
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* Board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.
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* J11 (Molex 878331031) on the back end connects via flat cable (Amphenol 191-2815-010) to J70 of SIS1160.
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* J11 (Molex 878331031) on the back end connects via flat cable (Amphenol 191-2815-010) to J70 of SIS1160.
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- Frontend: 6 digital channels (Lemo connectors)
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- Frontend: 6 digital channels (LEMO connectors)
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* 4 LVDS input/output ports (Lemo 00 triaxial connectors), non-isolated.
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* 4 LVDS input/output ports (LEMO 00 triaxial connectors), non-isolated.
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* 2 LVTTL input/output ports (Lemo 00 coaxial connectors), non-isolated
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* 2 LVTTL input/output ports (LEMO 00 coaxial connectors), non-isolated
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* Note that if the holes in the PCI bracket for the LEMO are too tight, you will need to isolate with wrap the LEMO connector sides to avoid breaking the galvanic isolation.
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- Predefined pin function on J1-J6 (add-on board) interfacing J70 (SIS1160 board):
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- Predefined pin function on J1-J6 (add-on board) interfacing J70 (SIS1160 board):
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* The direction of every pair/signal at J70 can be controlled individually.
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* The direction of every pair/signal at J70 can be controlled individually.
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* J1 <=> J70-[1,2]: [CLK_P, CLK_N] LVDS Synchronous clock source distribution
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* J1 <=> J70-[1,2]: [CLK_P, CLK_N] LVDS Synchronous clock source distribution
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