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# SIS1160 PCI-L I/O add on
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The *sis1160-pci-io* is a front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins of the [SIS1160 FMC carrier](https://www.struck.de/sis1160.html).
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This auxiliary board gets inserted in a computer, next to the SIS1160 carrier, with a PCI bracket (but does not use the PCI bus), and has 6 digital channels. Three of them are direct outputs from the SIS1160 carrier (LVDS). A fourth one (LVDS) is user-configurable (input or output). The two remaining channels (LVTTL) are input channels that are forwarded to the SIS1160 carrier.
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The *sis1160-pci-io* is a front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins (J70) of the [SIS1160 FMC carrier](https://www.struck.de/sis1160.html).
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This auxiliary board gets inserted in a computer, next to the SIS1160 carrier, with a PCI bracket (but does not use the PCI bus), and has 6 digital channels. Four of them are LVDS and two are LVTLL. The direction of every signal or pair can be configured to act as input or output from/into the SIS1160 carrier.
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The SIS1160 carrier board is used together with the [SFMC01](https://www.struck.de/sfmc01.html) digitizer, that contains the [AD9689](https://www.analog.com/en/products/ad9689.html) analog-to-digital converter. The current repository features thus an auxiliary board that allows the integration of "events" or "GPIO markers" into the ADC datastream. The lower bits of the acquired ADC data words can be configured (via the SIS1160 API) to store the status of the input channels of the PCI-L I/O add on. Furthermore, the 3 output channels can be used for monitoring the trigger or clock and synchronizing with additional external hardware.
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The SIS1160 carrier board is used together with the [SFMC01](https://www.struck.de/sfmc01.html) digitizer, that contains the [AD9689](https://www.analog.com/en/products/ad9689.html) analog-to-digital converter. The current repository features thus an auxiliary board that allows the integration of "events" or "GPIO markers" into the ADC datastream. The lower bit of the acquired ADC data word of each ADC channel can be configured (via the SIS1160 API) to store the status of two selected input channels of the PCI-L I/O add on. Furthermore, the other (output) channels can be used for monitoring the trigger or clock and synchronizing with additional external hardware.
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<img src="uploads/f957d394e561ec517bb4f0c4758f7584/PCB.png" height="400" title="PCI-L I/O add-on"> *I/O add-on* ------- *SIS1160* <img src="uploads/29406001d564d17be0d4c40868a36522/SIS1160.png" height="400" title="SIS1160 FMC carrier with interconnect">
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... | ... | @@ -14,8 +14,16 @@ The SIS1160 carrier board is used together with the [SFMC01](https://www.struck |
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* Board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.
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* J11 (Molex 878331031) on the back end connects via flat cable (Amphenol 191-2815-010) to J70 of SIS1160.
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- Frontend: 6 digital channels (Lemo connectors)
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* 3 LVDS output ports from J70, 1 LVDS input/output port (Lemo 00 triaxial connectors), non-isolated.
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* 4 LVDS input/output ports (Lemo 00 triaxial connectors), non-isolated.
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* 2 LVTTL input/output ports (Lemo 00 coaxial connectors), non-isolated
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- Predefined pin function on J1-J6 (add-on board) interfacing J70 (SIS1160 board):
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* The direction of every pair/signal at J70 can be controlled individually.
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* J1 <=> J70-[1,2]: [CLK_P, CLK_N] LVDS Synchronous clock source distribution
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* J2 <=> J70-[3,4]: [TRIG_P, TRIG_N] LVDS (Suggestion) Global trigger distribution, firmware defined
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* J3 <=> J70-[5,6]: [TIMES_P, TIMES_N] LVDS (Suggestion) Global timestamp distribution, firmware defined
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* J4 <=> J70-[7,8]: [USER1_P, USER1_N] LVDS General purpose
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* J5 <=> J70-[9]: [USER2_L] LVTTL General purpose, single ended, open drain
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* J6 <=> J70-[10]: [USER3_L] LVTTL General purpose, single ended, open drain
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- Programmable termination on SIS1160 via switch SW70:
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* SW70-1: When ON, enable 100Ω Termination for CLK_P/CLK_N
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* SW70-2: When ON, enable 100Ω Termination for TRIG_P/TRIG_N
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