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SDB - Self-describing Bus

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Last edited by OHWR Gitlab support
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Overview

The idea of a self-description for a bus appeared while working on White Rabbit and related projects that make massive use of FPGA devices. Separately and concurrently, both the CERN and the GSI working groups identified the need for some way to self-detect the contents of a specific logic device after it is programmed. We envisioned that if the internal FPGA bus could enumerate its own content, we would get a lot of advantages.

As usual in engineering, we wanted a system that was as simple as possible, yet open to future extensions without introducing compatibility issues. While our internal bus is Wishbone, we designed the structures to be generic so other
bus implementations may use them.

The Self Description Bus allows to enumerate the cores that are live in the current fpga binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. It is also used as a simple filesystem in our EEPROM devices, so data can be easily accessed by both the host and the soft core that lives in the FPGA itself.

The current specification is already in use in some of our designs.

Specification

Last Version: Document

In the document section you can find all the SDB specification version together with the header file. All the documents have been built with LaTex from the doc directory of the repository.

Support

We offer the following sources of support:

Please** read the documentation and then the FAQ) before asking for support on the mailing list.

Code

The implementation as VHDL is part of the respective projects.

Code for the Linux kernel (both as a bus driver and a file system driver) is being written. Available code is part of this repository, but it's still work in progress. Sdbfs is being used in our EEPROMs using the user-space tools and library currently in the "sdbfs" subdir of the repository

Guide Lines

For the VHDL implementation we have wrote a brief sdb implementation guidelines

Ongoing Discussions

Interrupts

We chose, for the time being, to not describe interrupts. After some drafts for one such description, Wesley Terpstra explained why legacy interrupts should be avoided in a SoC design and MSI-like interrupts don't need an external description. His complete reasoning is here: Interrupts

Status

Date Event
09-05-2011 Start of project
09-05-2011 Added draft of specification (available in Repository section)
10-05-2011 Added code for wishbone simulator (source code available in Repository or Files section)
21-06-2012 After long discussions, the specification is published
11-04-2013 Version 1.1 of the sdb specification, including sdbfs material and more
12-10-2014 SDB presented at the OpenRISC Conference 2014.
20-07-2015 SDB has now a dedicate project page