... | @@ -160,8 +160,8 @@ Controls the hardware trigger inside the FPGA. |
... | @@ -160,8 +160,8 @@ Controls the hardware trigger inside the FPGA. |
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*Functions:**
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*Functions:**
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\*`__init__(self, mem, addr)`: The builder. The different addresses are
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\*`__init__(self, mem, addr)`: The builder. The different addresses are
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0x1000 for channel 0, 0x3000 for channel 1, 0x5000 for channel 2 and
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: 0x1000 for channel 0, 0x3000 for channel 1, 0x5000 for channel 2 and
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0x8000 for channel 3.
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0x7000 for channel 3.
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\*`configure(self, edge, threshold_lo, threshold_hi, mask)`: Set the
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\*`configure(self, edge, threshold_lo, threshold_hi, mask)`: Set the
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trigger independently. Set the triggering edge (Rising edge if 0 and
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trigger independently. Set the triggering edge (Rising edge if 0 and
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Falling edge if 1). The two threshold levels are set here. Finally, the
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Falling edge if 1). The two threshold levels are set here. Finally, the
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... | @@ -170,3 +170,89 @@ mask is set to 0xF, this means that any event on any channel will |
... | @@ -170,3 +170,89 @@ mask is set to 0xF, this means that any event on any channel will |
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trigger the record on all the channels. Any other combination of trigger
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trigger the record on all the channels. Any other combination of trigger
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can be configured.
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can be configured.
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<table>
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<tbody>
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<tr class="odd">
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<td></td>
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<td><strong>Chan3</strong></td>
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<td><strong>Chan2</strong></td>
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<td><strong>Chan1</strong></td>
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<td><strong>Chan0</strong></td>
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</tr>
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<tr class="even">
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<td><strong>Trig0</strong></td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr class="odd">
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<td><strong>Trig1</strong></td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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</tr>
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<tr class="even">
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<td><strong>Trig2</strong></td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td><strong>Trig3</strong></td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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</tr>
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</tbody>
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</table>
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The table 1 shows an example of configuration. Each corresponds to a
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trigger mask. On this example, with its mask set to 0xF, an event on
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trigger0 will trigger the recording on all the channels. Trigger1, with
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a 0x6 mask, will trigger the recording on channel 2 and 1. An event on
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channel 2 will not trigger any recording as the mask is 0x0. And
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finally, an event occurring on channel 3 will only trigger the recording
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on its channel.
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\*`force(self)`: Used to force the trigger. Mainly used for debugging.
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\*`triggered(self)`: Return True if an eligible event occurred on this
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channel.
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\*`arm(self)`: Arm the trigger
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### Buffer
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This cyclical buffer is used to record the data. It is continuously
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recording the data. Once the pointer arrives at the end of the buffer,
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it starts recording since the very beginning. If an event is detected by
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a trigger, the pointer continues to write data but stops after looping
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avoiding erasing data arrived after the event. By stopping the pointer
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earlier, it is possible to save pretrigger samples.
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*Functions:**
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\*`__init__(self, mem, addr)`: The builder. The possible addresses are :
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0x2000 for channel 0, 0x4000 for channel 1, 0x6000 for channel 2 and
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0x8000 for channel 3.
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\*`set_pretrigger(self, pretrigger)`: Number of samples kept before the
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event.
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\*`start(self)`: Launch the continuous recording in the buffer.
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\*`ready(self)`: Returns True when the buffer data is ready to be
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transferred to the Ps.
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\*`read(self)`: Returns the formatted data out of the buffer. This needs
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the `sign_extend(value, bits)` global function used to format raw data.
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### AD9253
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This class is set for the ADC. It is basically represented by its SPI
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communication.
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\*Functions:\_
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\*`__init__(self, spi)`: The builder. It needs the SPI interface to be
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set.
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\*`write_reg(self, reg, value)`: It is used to write in the ADC
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registers.
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\*`read_reg(self, ref)`: Used to read a specific ADC register.
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