... | ... | @@ -27,43 +27,17 @@ elements are added. |
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## Acutal prototype features
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Parameter </b></td>
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<td><b> Value </b></td>
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</tr>
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<tr class="even">
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<td>channels</td>
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<td>4</td>
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</tr>
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<tr class="odd">
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<td>Precision</td>
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<td>< 5 ps RMS</td>
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</tr>
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<tr class="even">
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<td>Range</td>
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<td>10 ns</td>
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</tr>
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<tr class="odd">
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<td>Input pulse voltage</td>
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<td>2.31 V to 3.3 V</td>
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</tr>
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<tr class="even">
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<td>Measurements rate</td>
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<td>1.5 Hz</td>
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</tr>
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<tr class="odd">
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<td>Connectors</td>
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<td>SMA @ 50 ohm</td>
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</tr>
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<tr class="even">
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<td>Clock source</td>
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<td>Internal: 100 MHz oscillator<br />
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External: up to 125 MHz with an external clock</td>
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</tr>
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</tbody>
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</table>
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|**Parameter**|**Value**|
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|----|----|
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|channels|4|
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|Precision|< 5 ps RMS|
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|Range|10 ns|
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|Input pulse voltage|2.31 V to 3.3 V|
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|Measurements rate|1.5 Hz|
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|Connectors|SMA @ 50 ohm|
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|Clock source|Internal: 100 MHz oscillator
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External: up to 125 MHz with an external clock|
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The "brain" of the system is a
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[MicroZed](http://zedboard.org/product/microzed) FPGA prototyping board.
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... | ... | @@ -135,78 +109,25 @@ The used ADC is the Analog Devices |
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>01-02-2016</td>
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<td>Start working on project.</td>
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</tr>
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<tr class="odd">
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<td>15-02-2016</td>
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<td>Starting the first ADC board Design</td>
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</tr>
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<tr class="even">
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<td>05-03-2016</td>
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<td>Finishing the first Design</td>
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</tr>
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<tr class="odd">
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<td>05-03-2016</td>
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<td>Starting the layout of the first ADC board</td>
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</tr>
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<tr class="even">
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<td>12-04-2016</td>
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<td>Presentation of the project, design and layout at CERN</td>
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</tr>
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<tr class="odd">
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<td>15-04-2016</td>
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<td>Full design and layout review at CERN</td>
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</tr>
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<tr class="even">
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<td>15-05-2016</td>
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<td>Start to update the schematics</td>
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</tr>
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<tr class="odd">
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<td>03-06-2016</td>
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<td>Schematic updated. Wait for review</td>
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</tr>
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<tr class="even">
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<td>21-06-2016</td>
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<td>Review of the schematics</td>
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</tr>
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<tr class="odd">
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<td>27-06-2016</td>
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<td>Starting new layout</td>
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</tr>
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<tr class="even">
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<td>05-07-2016</td>
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<td>Layout finished. Waiting for review</td>
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</tr>
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<tr class="odd">
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<td>13-07-2016</td>
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<td>Layout Review at CERN</td>
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</tr>
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<tr class="even">
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<td>02-08-2016</td>
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<td>Layout corrected, first prototype ordered</td>
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</tr>
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<tr class="odd">
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<td>16-09-2016</td>
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<td>PCB mounted arrived and ready for debug</td>
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</tr>
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<tr class="even">
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<td>21-09-2016</td>
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<td>Low noise filter build, tests started</td>
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</tr>
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<tr class="odd">
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<td>07-10-2016</td>
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<td>RMS error on the measurements : 3 ps</td>
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</tr>
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</tbody>
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</table>
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|**Date**|**Event**|
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|----|----|
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|01-02-2016|Start working on project.|
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|15-02-2016|Starting the first ADC board Design|
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|05-03-2016|Finishing the first Design|
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|
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|05-03-2016|Starting the layout of the first ADC board|
|
|
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|12-04-2016|Presentation of the project, design and layout at CERN|
|
|
|
|15-04-2016|Full design and layout review at CERN|
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|
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|15-05-2016|Start to update the schematics|
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|03-06-2016|Schematic updated. Wait for review|
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|21-06-2016|Review of the schematics|
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|27-06-2016|Starting new layout|
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|05-07-2016|Layout finished. Waiting for review|
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|13-07-2016|Layout Review at CERN|
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|02-08-2016|Layout corrected, first prototype ordered|
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|16-09-2016|PCB mounted arrived and ready for debug|
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|21-09-2016|Low noise filter build, tests started|
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|07-10-2016|RMS error on the measurements : 3 ps|
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[Detailed-Status](Detailed-Status)
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... | ... | @@ -214,3 +135,4 @@ The used ADC is the Analog Devices |
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8th of November 2016 - Nicolas Boucquey
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