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# Multi-channel Time Interval Counter and fine delay generator
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## Project description
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Multi-channel Time Interval Counter and fine delay generator. Based on
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measurement of a voltage ramp, housed in 19" module. Research project.
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*TEMPLATE TEXT BELOW**
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The FMC DEL 1ns 4cha *delay module* will take in a TTL trigger signal
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and will send it out to four different outputs. The delay from the
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trigger input to each of the outputs can be set independently in a range
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from 600 ns to 120 seconds. It is implemented using a dedicated
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time-to-digital converter IC from the European company
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[Acam](http://www.acam.de/index.php?id=22&L=0).
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[![](/project/fmc-delay-1ns-8cha/uploads/a619d95e21b84c80ccd8eceb5dbb7caa/delay-v5-small.jpg)](/project/fmc-delay-1ns-8cha/uploads/bd03006106ad4b9aa220ac35dd0ec1f6/delay-v5-big.jpg)
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*Top view of the FMC Delay card**
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[Bottom view
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(prototype)](https://www.ohwr.org/project/fmc-delay-1ns-8cha/uploads/5e2716e782e548bd1cfa3edface5f45c/proto_side_b_s.JPG)
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-----
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## Specifications
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- Full details in the [Functional system
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specifications](FmcDelFuncSpec)
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### Specification overview
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Parameter</strong></td>
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<td><strong>Value</strong></td>
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</tr>
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<tr class="even">
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<td>Channels</td>
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<td>1 trigger input, 4 outputs</td>
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</tr>
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<tr class="odd">
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<td>Signal connectors</td>
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<td>LEMO 00 for all signals</td>
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</tr>
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<tr class="even">
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<td>FMC connector</td>
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<td>Low Pin Count (LPC)</td>
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</tr>
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<tr class="odd">
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<td>Signal level</td>
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<td>TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate</td>
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</tr>
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<tr class="even">
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<td>Operating modes</td>
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<td><strong>Pulse delay</strong>: on trigger, generates a pulse or series of pulses of given width and repetition rate on chosen outputs after a certain time programmed by the user.<br />
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<strong>Single channel TDC</strong>: time tags incoming trigger pulses available via a circular buffer.<br />
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<strong>Pulse generator</strong>: produces a pulse or a series of pulses of arbitrary length and repetition rate starting at a given UTC/TAI time.</td>
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</tr>
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<tr class="odd">
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<td>Minimum input pulse width</td>
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<td>100 ns. Pulses below 24 ns are ignored.</td>
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</tr>
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<tr class="even">
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<td>Maximum input pulse rate</td>
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<td>1 MHz (minimum pulse spacing: 1 us)</td>
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</tr>
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<tr class="odd">
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<td>Output pulse width</td>
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<td>250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution)</td>
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</tr>
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<tr class="even">
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<td>Output pulse spacing</td>
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<td>250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution)</td>
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</tr>
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<tr class="odd">
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<td>Trigger to output delay</td>
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<td>600 ns (min) to 120 seconds (max). Independent setting for each channel.</td>
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</tr>
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<tr class="even">
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<td>Output pulse repeat count (train generation)</td>
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<td>1 - 65536 pulses or infinity (continuous mode)</td>
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</tr>
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<tr class="odd">
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<td>Timebase accuracy</td>
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<td>± 2.5 ppm<br />
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The timebase from a local TCXO on FMC card needs calibration. The 2.5 ppm accuracy is the one of the on-board TCXO. Cesium-quality accuracy will be reached when used on a <a href="https://www.ohwr.org/project/white-rabbit/wiki">White Rabbit</a> enabled FMC carrier.</td>
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</tr>
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<tr class="even">
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<td>TDC Resolution</td>
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<td>28 ps</td>
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</tr>
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<tr class="odd">
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<td>TDC Precision (std. dev)</td>
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<td>55 ps</td>
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</tr>
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<tr class="even">
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<td>Delay accuracy</td>
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<td>Baseline: < 300 ps average, < 1 ns peak-to-peak (minimum delay setting of 600 ns).<br />
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Accuracy is as good as the time base, e.g. for a delay of 1 s using internal time base, the worst case error will be (2.5 ppm x 1 s) = 2.5 us. The accuracy can be greatly improved by locking the card to GPS/Cesium clock source through [White Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/).</td>
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</tr>
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<tr class="odd">
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<td>Time tag buffer</td>
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<td>1024-entries circular buffer with time tags for input/output pulses. Buffer interrupt (with timeout/threshold coalescing)</td>
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</tr>
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<tr class="even">
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<td>Power consumption</td>
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<td>7 Watt (200 mA from 12V, 1.5 A from 3V3)</td>
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</tr>
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</tbody>
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</table>
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-----
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## Detailed project information
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- **Official production documentation (schematics, PCB, etc.):**
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[EDMS: EDA-02267](http://edms.cern.ch/nav/EDA-02267)
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- [Users](Users)
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- [Software](Software)
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- [CERN specific information](CERN)
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- [Driver developers information](Driver-developers-information)
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- [Notes on hardware/VHDL design](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/Documents/Hardware-and-VHDL-design-notes)
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- [User's manual](https://www.ohwr.org/project/fine-delay-sw/wikis/Documents/HW/SW-manual-for-release-1.1)
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- [Long term test report](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/Documents/Long-term-test-report)
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- [Temperature issues and solutions](Temperature-Issues)
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- [Frequently Asked Questions](FAQ)
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-----
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## Releases
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- Hardware: FMC Delay 1ns 4cha -
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[EDA-02267-V6-1](https://edms.cern.ch/nav/EDA-02267-V6-1)
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- Gateware: [Releases](releases) page.
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- Linux driver: see [Software support for FMC
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Delay 1ns 4cha](https://www.ohwr.org/project/fine-delay-sw/wiki)
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(Project)
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-----
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## Contacts
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### Commercial producers
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- [Fine
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Delay](http://www.incaacomputers.com/component/resource/article/products/by-function/17-timing-gen/169-fine-delay)
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- [INCAA Computers](http://incaacomputers.nl), Netherlands
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- [Fine Delay](http://www.sevensols.com/en/products/fmc-del.html) -
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[Seven Solutions](http://www.sevensols.com/index.php), Spain
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>01-02-2016</td>
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<td>Start working on project.</td>
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</tr>
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</tbody>
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</table>
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-----
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18 February 2016
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