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This core is a QDRII controller with two pipelined Wishbone slave
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ports.
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It is based on the Virtex-6 hardware core and a management core for
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QDRII+ generated by Xilinx CoreGen.
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QDRII+ generated by Xilinx
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CoreGen.
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# Overview
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\!QDRII\_controller diagramv0.jpg\!
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![](/uploads/b71717fde3e37ed76ba2c19334b90c60/QDRII_controller_diagramv0.jpg)
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## QDRII controller developing steps:
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