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# Proyect Description
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This core is a QDRII controller with two pipelined Wishbone slave
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ports.
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It is based on the Virtex-6 hardware core and a management core for
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QDRII+ generated by Xilinx CoreGen.
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# Overview
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\!QDRII\_controller diagramv0.jpg\!
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## QDRII controller developing steps:
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\# Writing VHDL code and functional test for QDRII memory controller
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(based on QDRII+ MIG from Xilinx) **Completed**
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\#\# Generation of QDRII+ memory interface from Xilinx Core Generator
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(ISE 13.1). QDRII+ is supported by MIG (Memory interface Generator) but
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not QDRII. (doc: “UG406.Virtex-6 FPGA Memory Interface Solutions”)
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\#\# Functional test simulated and internal understanding of the
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generated VHDL in part 1.1.
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\#\# Differences between QDRII devices and QDRII+ devices made us modify
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the provided code. (doc: “xapp886.Interfacing QDRII\_SRAM Devices with
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V6 FPGAs”)
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\* Modification of parameter values to adapt it to QDRII specifications.
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\* Modification of memory words burst. Following this QDRII
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specifications and datasheet: the QDRII is two-words burst whereas the
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given design is a four-words burst design. That involved:
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* Modify the W/R state machine to operate properly for two-words
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burst.
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* Modify the testbench to verify correct operation for two-words
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burst.
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\#\# Modify the generic testbench and verify the functional test for our
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QDRII memory CY7C1314CV18. For that purpose the verilog model provided
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by Cypress was downloaded and used. **Test completed and passed
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successfully**
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1. Once the SCBv3 was released, we tested and implemented in hardware
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the QDRII controller done in step 1. **(red) Completed**
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\#\# An ISE project was created in order to implement the memory
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controller inside de FPGA. In this design, we had to take into account
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temporal constrains and FPGA pins (following SCBv3 schematics). At
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first, the project did not work properly (no writing neither reading was
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properly done), we also noticed that the behaviour was different from
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simulation. Since it was quite difficult to find the problem with this
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amount of possibilities and variables, we decided to step back and start
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testing the hardware first (2.2 and 2.3 steps).
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\#\# To avoid hardware related problems (pin errors, short-circuits,
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clock problems,…), it was created another simple ISE project where the
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main QDRII tracks were tested with the Oscilloscope.
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\#\# Following the 2.2 step and the QDRII datasheet (CY7C1314CV18), we
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created a basic project where the reading and writing processes were
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done and successfully achieved. We checked the result with ChipScope
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(Xilinx tool that inserts logic analyzer, system analyzer, and virtual
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I/O low-profile software cores directly into the design, allowing us to
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view any internal signal or node “in real time”). Although this project
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proves the correct operation of the memory, it can not be used as a real
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controller since it is not efficient and the frequency used is too slow.
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If we try to increase frequency in order to use it more efficiently, we
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will start having problems with temporal constrains within internal FPGA
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track, PCB tracks and clock delays. This is out of the scope of this
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small and functional design.
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\#\# Once the PCB and hardware had been checked, we continued testing
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the project from step 2.1(QDRII controller based on MIG) in order to
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make it worked properly. For that reason we introduced the ChipScope
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analyzer inside this project, testing and checking all main signals in
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the design. Further tests provided that the problem was located in the
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calibration process, the delay in some tracks were out of the range, so
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the design could never start without these proper delays. Once it was
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fixed, we tested all memory addresses and data bits successfully.
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Bandwidth: 2 channel of 72 data bits for writing and reading
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simultaneously over a frequency of 100MHz or, in order words, it is
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possible to write and read 72 bits from/to the memory in the same 200MHz
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cycle.
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\#\# Implementation and test of the second QDRII memory controller from
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SCB board. Modification of FPGA pins and minor changes inside the
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controller. **Test completed and passed successfully**
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1. Development of a bridge interface between the QDRII memory
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controller and wishbone bus. \* \*
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# Documents
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attachment:CY7C1314CV18.pdf CY7C1314CV18 – QDRII memory datasheet
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attachment:ug406.pdf ug406 – Virtex-6 FPGA Memory Interface Solutions
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attachment:xapp886.pdf xapp886 – Interfacing QDRII SRAM Devices with
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Virtex-6 FPGAs
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Check Xilinx website for latest version:
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http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig.htm
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Date </b></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>23-11-2011</td>
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<td>First simulation prototype (QDRII memory controller docs and code)</td>
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</tr>
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</tbody>
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</table>
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### Files
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* [CY7C1314CV18.pdf](/uploads/9c4ac2e7b1c984bd913fafa1e1347f37/CY7C1314CV18.pdf)
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* [ug406.pdf](/uploads/ce0faa4e38d3d605d140c8ec4cde59c7/ug406.pdf)
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* [xapp886.pdf](/uploads/3af02b0ca5af64a8afe70c7dcfda50c6/xapp886.pdf)
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* [QDRII_controller_diagramv0.jpg](/uploads/73be4991980a3e38886b6d73620e9271/QDRII_controller_diagramv0.jpg) |
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\ No newline at end of file |