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QDRII+ generated by Xilinx
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CoreGen.
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# Overview
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![](/uploads/b71717fde3e37ed76ba2c19334b90c60/QDRII_controller_diagramv0.jpg)
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h2. QDRII controller developing steps:
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# Overview
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![](/uploads/b71717fde3e37ed76ba2c19334b90c60/QDRII_controller_diagramv0.jpg)
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## QDRII controller developing steps:
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\# Writing VHDL code and functional test for QDRII memory controller
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(based on QDRII+ MIG from Xilinx) **Completed**
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