... | @@ -14,7 +14,7 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
... | @@ -14,7 +14,7 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
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- Compliance with [PXIe standard for 3U system controller slot](http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF)
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- Compliance with [PXIe standard for 3U system controller slot](http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF)
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- PCIe lane designed to meet PCIe GEN 3 specification
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- PCIe lane designed to meet PCIe GEN 3 specification
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- 16x PCIe lanes routed to the PXIe backplane connector
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- 16x PCIe lanes routed to the PXIe backplane connector
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- PXIe trigger controller (FPGA)
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- PXI trigger controller (FPGA)
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- Possibility to install a full size mSATA SSD (supports mini mSATA)
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- Possibility to install a full size mSATA SSD (supports mini mSATA)
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- Front panel
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- Front panel
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- 1x RS232 port DSUB9 connector
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- 1x RS232 port DSUB9 connector
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... | @@ -22,7 +22,7 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
... | @@ -22,7 +22,7 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
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- 2x USB 3.0
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- 2x USB 3.0
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- 1x 10/100/1000 Ethernet LAN
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- 1x 10/100/1000 Ethernet LAN
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- 1x DisplayPort
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- 1x DisplayPort
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- 1x SMB PXIe trigger line
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- 1x SMB Trigger line
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- Xilinx XC7A50T-1FTG256C FPGA for trigger management
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- Xilinx XC7A50T-1FTG256C FPGA for trigger management
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