PXIe Communication Tester - PXCT
Project description
Tester board for testing PXIe processor modules in a PXIe chassis.
It comes in two variants: slot 2 and slot 10 (system timing slot).
This auxiliary test board will be used to test the COM port, front panel trigger and the PXI bus signals. Two types of this new board will be installed. One in slot 2 (next to the the processor board, like the PXIeCOMe, the other in slot 10 (the system timing slot).
It has a front panel COM port (SubD9) through which it can be controlled by the PXIeCOMe COM port, and so can be used to also test the COM port of the PXIeCOMe.
It can be controlled using a serial GPIB like command set similar to the PXIeCOMe_tFPGA (Xilinx Vivado design for the hardware debugging project, and also used for the PTS project), but this auxiliary test board will be using an ARM Cortex-M3 microcontroller.
TEMPLATE DATA BELOW - PLEASE MODIFY*
Main Features
- Compliance with COM Express basic Pin-out type 6
- Heat spreader allows for 42 Watt dissipation in airflow of 1.0 - 1.5 m/s
- Compliance with PXIe standard for 3U system controller slot
- PCIe lane designed to meet PCIe GEN 3 specification
- 16x PCIe lanes routed to the PXIe backplane connector
- PXIe trigger controller (FPGA)
- Possibility to install a full size mSATA SSD (supports mini mSATA)
- Front panel
- 1x RS232 port DSUB9 connector
- 4x USB 2.0
- 2x USB 3.0
- 1x 10/100/1000 Ethernet LAN
- 1x DisplayPort
- 1x SMB PXIe trigger line
- Xilinx XC7A50T-1FTG256C FPGA for trigger management
Project information
- Official production documentation
- PXIe controller COM Express based carrier Design Study
- Schematics
- Users
- Software
- Frequently Asked Questions
Contacts
Commercial producers
- Foreseen to be commercially available once the development is finished.
General questions about project
- Paul Peronnard - CERN
- Erik van der Bij - CERN
Status
Date | Event |
---|---|
05-07-2021 | First specifications written. |
5 July 2021