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# Simple PCIe FMC carrier (SPEC)
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## Project description
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The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
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SFP connector. On the PCIe side it has a 4-lane interface, while the FMC
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mezzanine slot uses a low-pin count connector. This board is optimised
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for cost and is usable with most of the FMC cards designed within the
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OHR project (e.g. ADC cards, Fine Delay). The board is [commercially
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available](https://ohwr-gitlab.cern.ch/project/spec/wiki#commercial-producers).
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Labview and Linux drivers are available for the [FMC DEL 1ns 4cha
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delay](https://ohwr-gitlab.cern.ch/project/fmc-delay-1ns-8cha/wiki) and
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[FMC
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TDC 1ns 5cha](https://ohwr-gitlab.cern.ch/project/fmc-tdc/wiki)
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TDC mezzanine cards.
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Boards with a very similar architecture are available for the VME bus
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([SVEC - Simple VME FMC Carrier
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(SVEC)](https://ohwr-gitlab.cern.ch/project/svec/wiki)) and for the PXI
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Express bus ([SPEXI - Simple PXI express FMC Carrier Board
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(SPEXI)](https://ohwr-gitlab.cern.ch/project/spexi/wiki)).
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Other FMC projects and the FMC standard are described in [FMC
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Projects](https://ohwr-gitlab.cern.ch/project/fmc-projects).
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![](/project/spec/uploads/b3a055b61a0f902482488df868bb5665/spec_v1.1_top.JPG)
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*SPEC 1.1 first prototype**
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## Main Features
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- 4-lane PCIe (Gennum GN4124)
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C)
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- FMC slot with low pin count (LPC) connector
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- Vadj fixed to 2.5V
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- Clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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MHz (Silicon Labs Si570, freely usable)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://ohwr-gitlab.cern.ch/project/wr-cores/wikis/Wrpc-core))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://ohwr-gitlab.cern.ch/project/wr-cores/wikis/Wrpc-core))
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- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://ohwr-gitlab.cern.ch/project/wr-cores/wikis/Wrpc-core))
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- On board memory
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- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
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- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware or of critical data
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- Miscellaneous
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- on-board thermometer IC (DS18B20U+)
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- unique 64-bit identifier (DS18B20U+)
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- Front panel containing
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- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
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transceiver
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([WhiteRabbit](https://ohwr-gitlab.cern.ch/project/white-rabbit)
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support). 1.25 and 2.5 Gbps.
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- Programmable Red and Green LEDs
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- FMC front panel
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- Internal connectors
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- 1x JTAG header for Xilinx programming during debugging
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- 2x SATA connector
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- 1x mini USB AB (USB-UART bridge)
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- FPGA configuration. The FPGA can optionally be programmed from:
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- GN4124 SPRIO interface (loaded by software driver at startup)
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- JTAG header
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- SPI 32Mbit flash PROM
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- selectable by GN4124 GPIO. Default option would be loading via
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the SPI flash PROM (stand-alone applications).
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- Stand-alone features
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- External 12V power supply connector
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Power consumption: 5-12 Watt, depending on application
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- Optimised for cost
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- 6-layer PCB
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-----
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## Project information
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- Official production documentation: [EDMS
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EDA-02189](http://edms.cern.ch/nav/eda-02189)
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- CERN LHC Equipment name: CFEIA
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- [Controls Configuration Database
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entry](https://cs-ccr-oas1.cern.ch/pls/htmldb_dbabco/f?p=116:41:1087090489869201:GO:NO:RP:P41_QUERY,P41_CODE:YES,CFEIA)
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- [Controls EDMS
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page](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCFEIA___:V0/TAB4)
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- [Getting Started with the
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SPEC](https://ohwr-gitlab.cern.ch/project/spec-getting-started/wiki)
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(project)
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- [System architecture](SysArch)
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- [Users](Users)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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-----
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## Releases
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- Hardware: [SPEC
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V4](https://ohwr-gitlab.cern.ch/project/spec/wikis/documents)
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-----
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## Contacts
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### Commercial producers
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- [SPEC](http://www.creotech.pl/en/offer/white-rabbit/Simple_PCIe_FMC_carrier_SPEC)
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[Creotech](http://www.creotech.pl/en),
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Poland
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- [SPEC](http://www.incaacomputers.com/component/resource/article/Products/Products%20by%20application/6-Scientific/193-spec)
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[INCAA Computers](http://incaacomputers.nl),
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Netherlands
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- [SPEC](http://www.sevensols.com/index.php?seccion=1410&subseccion=1432&lang=en)
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[Seven Solutions](http://www.sevensols.com/index.php), Spain
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<!-- end list -->
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- Related products:
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- [SPEC BOX - 1 or 3 Standalone Nodes
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Box](http://www.sevensols.com/en/products/spec-box.html) [Seven
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Solutions](http://www.sevensols.com/index.php), Spain
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- SPEC100 - with larger XC6SLX100T FPGA [Seven
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Solutions](http://www.sevensols.com/index.php), Spain
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### General questions about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>22-06-2010</td>
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<td>Start of project. Design is done by an external company, based on the <a href="https://ohwr-gitlab.cern.ch/project/fmc-pci-carrier">FMC PCIe Carrier</a>.<br />
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Reviewing will be done by CERN.</td>
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</tr>
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<tr class="odd">
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<td>29-06-2010</td>
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<td>Main features reviewed by JS, PA, MC & EB. Design can start.</td>
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</tr>
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<tr class="even">
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<td>12-07-2010</td>
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<td>First schematics published. Ready for review.</td>
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</tr>
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<tr class="odd">
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<td>10-09-2010</td>
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<td>Review comments integrated. Start of PCB layout.</td>
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</tr>
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<tr class="even">
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<td>05-10-2010</td>
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<td>PCB layout review held.</td>
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</tr>
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<tr class="odd">
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<td>05-11-2010</td>
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<td>Design finished.</td>
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</tr>
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<tr class="even">
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<td>19-01-2011</td>
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<td>Three prototypes arrived at CERN.</td>
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</tr>
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<tr class="odd">
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<td>18-04-2011</td>
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<td>First V1.1 prototypes received, start testing them.</td>
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</tr>
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<tr class="even">
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<td>01-07-2011</td>
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<td>Three V2 boards received. One fully tested OK. Two only shortly tested.</td>
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</tr>
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<tr class="odd">
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<td>17-07-2011</td>
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<td>Order placed for 70 SPEC cards at Seven Solutions.</td>
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</tr>
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<tr class="even">
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<td>23-08-2011</td>
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<td>V4 released. Solves a minor mechanical problem with the SFP connector.</td>
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</tr>
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<tr class="odd">
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<td>14-03-2012</td>
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<td>CERN accepted the 10 preseries boards that were received on 7 March.</td>
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</tr>
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<tr class="even">
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<td>12-06-2012</td>
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<td>SPEC boards passed most restrictive EMC tests for industrial and domestic classes. [Test report](https://ohwr-gitlab.cern.ch/project/spec/wikis/Documents/EMC-Test-report).</td>
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</tr>
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<tr class="odd">
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<td>13-06-2012</td>
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<td>Board available from three commercial producers.</td>
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</tr>
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<tr class="even">
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<td>03-12-2013</td>
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<td>Labview Driver available for <a href="https://ohwr-gitlab.cern.ch/project/fmc-delay-1ns-8cha/wiki">FMC DEL 1ns 4cha</a> and [FMC TDC 1ns 5cha](https://ohwr-gitlab.cern.ch/project/fmc-tdc/wiki).</td>
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</tr>
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</tbody>
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</table>
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[Complete status](complete-status)
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-----
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 28 July 2014
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