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# Simple PCIe FMC carrier (SPEC)
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# pcie-fmc-soc-vdas
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## Project description
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pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine
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Card (VITA 57).
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The main component is a SOC chip used in cellular base stations that can
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do advanced processing.
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[More info at the Wiki
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page](https://ohwr-gitlab.cern.ch/project/pcie-fmc-soc-vdas/wiki)
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* Template text ****
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The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
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SFP connector. On the PCIe side it has a 4-lane interface, while the FMC
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mezzanine slot uses a low-pin count connector. This board is optimised
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... | ... | @@ -87,14 +96,6 @@ Projects](https://ohwr-gitlab.cern.ch/project/fmc-projects). |
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- Official production documentation: [EDMS
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EDA-02189](http://edms.cern.ch/nav/eda-02189)
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- CERN LHC Equipment name: CFEIA
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- [Controls Configuration Database
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entry](https://cs-ccr-oas1.cern.ch/pls/htmldb_dbabco/f?p=116:41:1087090489869201:GO:NO:RP:P41_QUERY,P41_CODE:YES,CFEIA)
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- [Controls EDMS
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page](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCFEIA___:V0/TAB4)
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- [Getting Started with the
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SPEC](https://ohwr-gitlab.cern.ch/project/spec-getting-started/wiki)
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(project)
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- [System architecture](SysArch)
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- [Users](Users)
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- [Software](Software)
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... | ... | @@ -133,7 +134,7 @@ Projects](https://ohwr-gitlab.cern.ch/project/fmc-projects). |
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### General questions about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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- [Marcus Barrow](mailto:marcus_barrow@comcast.net)
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-----
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... | ... | @@ -209,9 +210,7 @@ Reviewing will be done by CERN.</td> |
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</tbody>
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</table>
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[Complete status](complete-status)
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-----
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 28 July 2014
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Marcus Barrow - 7 November 2014
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