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## Abstract
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The board is called TTC\_FMC, it is an FMC card that plays the role of a
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TTC receiver (together with the associatd FPGA firmware). Its mjor
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components are a commercial clock/recovery IC, an optical receiver with
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FC connector and an SFP+ cage. The boards also offers two coaxial I/O
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connectors (LEMO series 00).
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An FPGA Mezzanine Card (FMC) for clock & data recovery (CDR) from
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optical sources. Its major components are a commercial clock/recovery
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IC, an optical receiver with FC connector and an SFP+ cage. The boards
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also offers two coaxial I/O connectors (LEMO series 00). The FMC is
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often referred-to as TTC FMC since it can play the role of Timing
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Trigger and Control (TTC) receiver for particle physics applications
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(together with the associated FPGA firmware).
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## Summary
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The Gigabit Link Interface Board (GLIB) is an evaluation platform and an
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easy entry point for users of high speed optical links in high energy
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physics experiments. Its intended use ranges from optical link
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evaluation in the laboratory to control, triggering and data acquisition
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from remote modules in beam or irradiation tests. The GLIB is a mid-size
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double-width Advanced Mezzanine Card (AMC) conceived to serve a small
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and simple system residing either inside a μTCA crate or on a bench with
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a link to a PC. Each GLIB card can process data to/from four SFP+
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transceiver modules, each operating at bi-directional data rates of up
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to 6.5Gbps since it is based on a high-performance Virtex-6 FPGA with
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twenty 6.5Gbps transceivers. This performance matches comfortably the
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specifications of the GBT/Versatile Link project with its targeted data
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rate of 4.8Gbps. In its simplest form, one GLIB board thus interfaces
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with up to four GBT channels. The GLIB I/O capability can be further
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enhanced with two FPGA Mezzanine Cards (FMCs).The two high-pin-count FMC
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sockets each provide up to 80 user-specific differential I/O pairs
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directly connected to the FPGA as well as two differential clock inputs
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and two differential clock outputs. The primary FMC also provides four
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optional 6.5Gbps transceiver lines, thus allowing extending the high
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speed serial I/O capability. Concerning the AMC high speed serial
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connectivity, the GLIB provides two Gigabit Ethernet (GbE) and two 2nd
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generation four-lane PCI Express (PCIe Gen2 4x) interfaces. It is
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important to mention that the GLIB gives users the possibility of
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implementing various other high speed serial data protocols (for custom
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applications) instead of PCIe. This is possible mainly thanks to GLIB’s
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sophisticated clock distribution circuitry that is based on cross-point
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switches and programmable clock multipliers. This circuitry offers a
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large selection of input clock sources (AMC clocks, FMC clocks, front
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panel clock connector or on-board oscillators). The GLIB also carries a
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GbE PHY as well as an Ethernet plug in order to interface to a PC
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through a standard Ethernet cable, while in bench-top operation. For
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temporary data storage, two 72Mb SRAM devices are available on-board.
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The GLIB has the possibility of using higher capacity (up to ~1Gb) SRAM
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devices once they become available. It is important to note that the two
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SRAMs have independent address/data buses. For configuration purposes, a
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very flexible Joint Test Action Group (JTAG) circuitry based on a
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Complex Programmable Logic Device (CPLD) is also available. The CPLD
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acts as a JTAG switch selecting the JTAG master source between the
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dedicated JTAG connectors, MMC or AMC JTAG lines for the configuration
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of the FPGA and the associated EEPROM. The JTAG switch is also useful
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for boundary scan testing purposes.
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A picture of the GLIB is shown below:
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![](/project/glib/uploads/dbac35a73829ae020390359f71b01570/glib.v2.png)
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