... | ... | @@ -4,15 +4,14 @@ An FPGA Mezzanine Card (FMC) for clock & data recovery (CDR) from |
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optical sources has been developed at CERN. Its major components are a
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commercial clock/recovery IC, an optical receiver with FC connector and
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an SFP+ cage. The boards also offers two coaxial I/O connectors (LEMO
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series 00). The FMC is also referred-to as TTC FMC since its main
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series 00). The FMC is often referred-to as TTC FMC since its main
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purpose is to play the role of Timing Trigger and Control (TTC) receiver
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for particle physics applications (together with the associated FPGA
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firmware).
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A block diagram of the TTC FMC is shown
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below:
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A diagram of the TTC FMC is shown below:
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![](/uploads/b5caceacc977c173fa81925a0cfd2c8f/ttc_fmc.block.small.png)
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ttc\_fmc.block.png
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A picture of the TTC FMC is shown
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below:
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