Folder structure example

MyProj
     |
     |-circuit_board
     |-doc
     |-hdl
     |   |-ip_cores 
     |   |        |-wr-cores      (submodule)
     |   |        |-general-cores (submodule)
     |   |
     |   |-platform
     |   |        |-Xilinx
     |   |        |-Altera
     |   |
     |   |-rtl
     |   |   |-
     |   |   |-moduleX
     |   |   |-moduleY
     |   |           |-wb_desc_file_y.wb
     |   |           |-wb_vhdl_file_y.vhd
     |   |           |-wb_vhld_file_y_pkg.vhd
     |   |   |-moduleZ
     |   |           |-wb_desc_file_x.wb
     |   |           |-wb_vhdl_file_x.vhd
     |   |           |-wb_vhld_file_x_pkg.vhd
     |   |
     |   |-syn
     |   |    |-myStuff
     |   |          |-Manifest.py
     |   |          |-top_z.xise
     |   |     
     |   |
     |   |-testbench
     |   |         |-include
     |   |         |       |-regs
     |   |         |       |    |-wb_vhdl_file_x.vh
     |   |         |       |    |-wb_vhdl_file_y.vh0
     |   |         |       |-model_x
     |   |         |       |-model_y
     |   |         |-testMyStuff
     |   |         |           |-myStuff.svh
     |   |         |-testModuleOfMyStuff
     |   |         |           |-testModule.svh
     |   |-top
     |   |    |-svec
     |   |         |-Manifest.py
     |   |         |-svec_top.vhd
     |   |         |-svec_top.ucf
     |   |    |-myBoard
     |
     |-software
     |        |-FPGA
     |        |-embedded
     |        |-host
     |-mechanics

reference:
https://www.ohwr.org/project/fmc-delay-1ns-8cha/tree/master

14 November 2017