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First version of talk for Soleil.

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% $Header: /cvsroot/latex-beamer/latex-beamer/solutions/conference-talks/conference-ornate-20min.en.tex,v 1.7 2007/01/28 20:48:23 tantau Exp $
\documentclass{beamer}
% This file is a solution template for:
% - Talk at a conference/colloquium.
% - Talk length is about 20min.
% - Style is ornate.
% Copyright 2004 by Till Tantau <tantau@users.sourceforge.net>.
%
% In principle, this file can be redistributed and/or modified under
% the terms of the GNU Public License, version 2.
%
% However, this file is supposed to be a template to be modified
% for your own needs. For this reason, if you use this file as a
% template and not specifically distribute it as part of a another
% package/program, I grant the extra permission to freely copy and
% modify this file as you see fit and even to delete this copyright
% notice.
\mode<presentation>
{
\usetheme{Warsaw}
% or ...
\setbeamercovered{transparent}
% or whatever (possibly just delete it)
}
\usepackage[english]{babel}
% or whatever
\usepackage {hyperref}
\usepackage[latin1]{inputenc}
% or whatever
\usepackage{times}
\usepackage[T1]{fontenc}
% Or whatever. Note that the encoding and the font should match. If T1
% does not look nice, try deleting the line with the fontenc.
\title[White Rabbit and common HW platform] % (optional, use only with long paper titles)
{White Rabbit Time Distribution System and Common Platform for Machine Instrumentation}
\subtitle{Plus some reflections on Open Hardware}
\author%[] % (optional, use only with lots of authors)
{J. Serrano}
% - Give the names in the same order as the appear in the paper.
% - Use the \inst{?} command only if the authors have different
% affiliation.
\institute%[Universities of Somewhere and Elsewhere] % (optional, but mostly needed)
{
%\inst{1}%
BE-CO Hardware and Timing section\\
CERN, Geneva, Switzerland
%\and
%\inst{2}%
%Department of Theoretical Philosophy\\
%University of Elsewhere
}
% - Use the \inst command only if there are several affiliations.
% - Keep it simple, no one is interested in your street address.
\date%[CFP 2003] (optional, should be abbreviation of conference name)
{Soleil, 30 June 2010}
% - Either use conference name or its abbreviation.
% - Not really informative to the audience, more for people (including
% yourself) who are reading the slides online
%\subject{Theoretical Computer Science}
% This is only inserted into the PDF information catalog. Can be left
% out.
% If you have a file called "university-logo-filename.xxx", where xxx
% is a graphic format that can be processed by latex or pdflatex,
% resp., then you can add a logo as follows:
%\pgfdeclareimage[height=1cm]{ohr-logo}{ohr_logo.jpg}
%\logo{\pgfuseimage{ohr-logo}}
% Delete this, if you do not want the table of contents to pop up at
% the beginning of each subsection:
\AtBeginSection[]
{
\begin{frame}<beamer>{Outline}
\tableofcontents[currentsection]
\end{frame}
}
% If you wish to uncover everything in a step-wise fashion, uncomment
% the following command:
%\beamerdefaultoverlayspecification{<+->}
\begin{document}
\begin{frame}
\titlepage
\end{frame}
\begin{frame}{Outline}
\tableofcontents
% You might wish to add the option [pausesections]
\end{frame}
% Structuring a talk is a difficult task and the following structure
% may not be suitable. Here are some rules that apply for this
% solution:
% - Exactly two or three sections (other than the summary).
% - At *most* three subsections per section.
% - Talk about 30s to 2min per frame. So there should be between about
% 15 and 30 frames, all told.
% - A conference audience is likely to know very little of what you
% are going to talk about. So *simplify*!
% - In a 20min talk, getting the main ideas across is hard
% enough. Leave out details, even if it means being less precise than
% you think necessary.
% - If you omit details that are vital to the proof/implementation,
% just say so once. Everybody will be happy with that.
\section{Requirements}
\begin{frame}{Desirable HW features of a distributed control system}{1/2}
\begin{block}{The good things of custom HW}
\begin{itemize}
\item
Function is exactly what you need.
\item
Can change easily if you find a bug. Or have it changed!
\item
Peer review. Potential for really good designs.
\item
Not tied to a single company (you never know).
\end{itemize}
\end{block}
\begin{block}{The good things of commercial HW}
\begin{itemize}
\item
Designed, built and tested by someone else (resource gain).
\item
Immediately available.
\item
Hardware proven by many users in many different applications.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Desirable HW features of a distributed control system}{2/2}
\begin{block}{Modular}
\begin{itemize}
\item
Re-use components easily.
\item
Have different people in an organization do what they do best.
\end{itemize}
\end{block}
\begin{block}{Interconnect!}
\begin{itemize}
\item
Allows to build distributed systems easily.
\item
Based on communication standards.
\item
Good sync capabilities. Transparent common notion of time.
\end{itemize}
\end{block}
\end{frame}
\section{Common platform for machine instrumentation}
\subsection{Introduction}
\begin{frame}{Background}
%the standard kit
\begin{itemize}
\item CERN's BE Controls group supports a kit of standard hardware modules.
\item Support includes stocks management, help in debugging and low level software:
\begin{itemize}
\item Linux Device Drivers.
\item C/C++ libraries with usage examples.
\item Test programs for drivers and libraries.
\end{itemize}
\item With the injectors renovation project, supported platforms will include PCI and PCIe in addition to VME.
\item A carrier/mezzanine strategy has been adopted.
\end{itemize}
\end{frame}
\begin{frame}{Advantages of the carrier/mezzanine approach}
\begin{block}{Re-use}
One mezzanine can be used in VME, PCI and PCIe carriers.
\end{block}
%\vspace{0.1cm}
\begin{block}{Reactivity}
No need to place and route a complex FPGA PCB for every new user need.
\end{block}
%\vspace{0.1cm}
\begin{block}{Rational split of work}
Controls can design the carrier, Instrumentation an ADC mezzanine, RF a DDS one, etc.
\end{block}
\end{frame}
\subsection{The FMC standard}
\begin{frame}{Outline}
\begin{columns}
\begin{column}{5cm}
\begin{center}
\includegraphics[width=3.5cm]{../pictures/carrier.png}%
\end{center}
\end{column}
\begin{column}{5cm}
\begin{center}
\includegraphics[width=3.5cm]{../pictures/single_width1.png}%
\end{center}
\end{column}
\end{columns}
Courtesy of VITA: http://www.vita.com/fmc.html
\end{frame}
\begin{frame}{Connectors}
\begin{center}
\includegraphics[width=\columnwidth]{../pictures/connector_fmc.png}%
\end{center}
\begin{itemize}
\item Ball Grid Array (BGA) characterized for high bandwidth applications.
\item Low Pin Count (LPC) and High Pin Count (HPC) variants with 160 and 400 contacts respectively.
\end{itemize}
\end{frame}
\begin{frame}{Physical Dimensions}
% \begin{columns}
% \begin{column}{5cm}
% \begin{center}
% \includegraphics[width=\columnwidth]{fmc_dimensions.png}%
% \end{center}
% \end{column}
% \begin{column}{5cm}
\begin{itemize}
\item Small dimensions for thermal reasons.
\item Keep all digital circuitry in the carrier.
\end{itemize}
% \end{column}
% \end{columns}
\end{frame}
\begin{frame}{Agnosticism}
\begin{itemize}
\item Pin function, sense -- input or output -- and electrical standard are defined at FPGA configuration time.
\item Carrier reads FMC identity through an I2C serial bus and configures the FPGA accordingly.
\end{itemize}
\end{frame}
\subsection{CERN's implementation}
\begin{frame}{Carrier design}
\begin{center}
\includegraphics[height=6cm]{../pictures/BoardBlockDiagramv2.pdf}%
\end{center}
\end{frame}
\begin{frame}{Ongoing developments}{1/2}
\begin{block}{Carriers}
\begin{itemize}
\item VME with two single-width (one double-width) slots.
\item PCIe with one single-width slot.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Ongoing developments}{2/2}
%\vspace{0.1cm}
\begin{block}{Mezzanines}
\begin{itemize}
\item Four-channel 100 MS/s 14-bit ADC with oscilloscope-type analog front end.
\item Eight-channel 100 kS/s 16-bit sampler.
\item Simple parallel digital I/O.
\item Under discussion:
\begin{itemize}
\item Four-channel 16-bit 120 MS/s sampler.
\item Four-channel 16-bit 120 MS/s DAC.
\item Clock generator based on 1 GS/s 32-bit DDS.
\item One-channel 24-bit 2 MS/s sampler.
\end{itemize}
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{A critique of FMC}{What we can say after 6 months of experience}
\begin{block}{Pros}
\begin{itemize}
\item It's a standard! Somebody thought hard about mechanics, dissipation, connectors...
\item The only agnostic standard for FPGA mezzanines.
\item Auto-discovery of card type very useful.
\end{itemize}
\end{block}
\begin{block}{Cons}
\begin{itemize}
\item Real estate a potential problem in some applications.
\item Little consideration given to Carrier-to-mezzanine clocks.
\end{itemize}
\end{block}
\begin{center}
Overall a good choice in our opinion.
\end{center}
\end{frame}
\begin{frame}{Use cases}
\begin{center}
\includegraphics[width=\columnwidth]{../pictures/use_cases.pdf}%
\end{center}
\end{frame}
\begin{frame}{Gateware and software}{Some initial ideas}
\begin{block}{Gateware}
\begin{itemize}
\item Internal bus is Wishbone-based (open standard with IP cores available).
\item Try to automate repetitive code through scripts.
\item Auto-discovery of Wishbone cores by Linux kernel would be nice.
\end{itemize}
\end{block}
\begin{block}{Software (very preliminary ideas!)}
\begin{itemize}
\item Define Wishbone as a bus in Linux.
\item Write Linux modules and interconnect them by a driver representing the whole board.
\item Integration into official kernel desirable.
\end{itemize}
\end{block}
\end{frame}
\subsection*{Part 1 Summary}
\begin{frame}{Part 1 Summary}
% Keep the summary *very short*.
\begin{itemize}
\item
The first \textbf{agnostic standard} to interface mezzanines and FPGAs.
\item
CERN's BE-CO group will adopt it to \textbf{improve support} of hardware and \textbf{reduce maintenance} costs.
\item
Combined with Open Hardware paradigm and collaborations, it can \textbf{reduce duplication} and \textbf{improve design quality}.
\end{itemize}
% The following outlook is optional.
\vskip0pt plus.5fill
\begin{itemize}
\item
Outlook
\begin{itemize}
\item
Finish carriers (and some mezzanines) designs before end 2010.
\item
Start collaboration with companies for series production of carriers and FMCs.
\end{itemize}
\end{itemize}
\end{frame}
\section{White Rabbit}
\subsection{Overview}
%\subsubsection{What is White Rabbit?}
% Layer 2 and it's for free - transparent. Data, sycchronism, determinism.
\begin{frame}{What is White Rabbit?}
\begin{center}
\includegraphics[height=6.5cm]{../pictures/rabbit.png}
\end{center}
\end{frame}
\begin{frame}{Design goals}
\begin{block}{Scalability}
Up to 2000 nodes.
\end{block}
\begin{block}{Range}
10 km fiber links.
\end{block}
\begin{block}{Precision}
1 ns time synchronization accuracy, 20 ps jitter.
\end{block}
\end{frame}
\begin{frame}{What is White Rabbit?}
% Extracting the clock from Ethernet carrier
\begin{block}{}
An \textbf{extension} to \textbf{Ethernet} which provides:
\begin{itemize}
% sync mode: - async & sync comparison, tree structure, common clock coming from single source, CDR
% advantage - easy and precise implementation of time sync
\item \textbf{Synchronous mode} (Sync-E) - common clock for physical layer in entire network, allowing for precise time and frequency transfer.
\item \textbf{Deterministic routing} latency - a guarantee that packet transmission delay between two stations will never exceed a certain boundary.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Network topology}
% data traffic - no hierarchy, timing traffic - hierarchy
\begin{center}
\includegraphics[height=6cm]{../pictures/hierarchy.pdf}%{./hierarchy.eps}
\end{center}
\end{frame}
\subsection{Technical concepts}
\begin{frame}{Technical concepts in White Rabbit}
\begin{itemize}
\item Synchronous Ethernet
\item Hardware-assisted PTP (IEEE1588 - Precision Time Protocol)
\item Packet preemption and deterministic protocol
\end{itemize}
\end{frame}
% Extracting clock from the data - timing idea applied to network.
% gigabit PHYs - easy to get good quality clock
\subsubsection{Synchronous Ethernet}
\begin{frame}{Synchronous Ethernet}
\begin{block}{Common clock for the entire network}
\begin{itemize}
\item All network nodes use the same physical layer clock, generated by the System Timing Master
\item Clock is encoded in the Ethernet carrier and recovered by the PLL in the PHY.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Synchronous Ethernet}
%passing the clock to the nodes lower in hierarchy
%cdr
\begin{center}
\includegraphics[height=6cm]{../pictures/synce.png}
\end{center}
\end{frame}
\subsubsection{PTP Protocol}
\frame{
\frametitle{PTP Protocol (IEEE1588)}
\begin{block}{PTP}
Synchronizes local clock with the master clock by measuring and compensating the delay introduced by the link.
\end{block}
\begin{center}
\includegraphics[height=4.5cm]{../pictures/phase_tracking.pdf}
\end{center}
}
\begin{frame}{Enhanced PTP}
\begin{itemize}
\item
Monitor phase of bounced-back clock continuously.
\item
Non-invasive: piggy backs on any type of traffic, including an idle link.
\item
Every 125 MHz tick is put to good use: performance is equivalent to PTP with messages exchanged every 8 ns.
\item Compatibility: works with any PTP-enabled network, but with superior performance in WR mode.
\end{itemize}
\end{frame}
\begin{frame}{Digital Dual Mixer Time Domain (DMTD) phase detector}
\begin{center}
\includegraphics[width=\columnwidth]{../pictures/dmtd.pdf}
\end{center}
\begin{itemize}
\item Fully digital, so fully linear.
\item In a loop, it becomes a linear phase shifter.
\end{itemize}
\end{frame}
\subsubsection{The WR protocol}
\begin{frame}{The WR protocol}
\begin{center}
\includegraphics[height=2cm]{../pictures/protocol.pdf}
\end{center}
\begin{itemize}
\item
Traffic divided into High Priority (HP) packets and Standard Priority (SP) packets.
\item
HP packets use a special value in the Ethertype field of the frame.
\item Quality of Service (QoS) in the 802.1Q VLAN standard does this and more $\Rightarrow$ will study full compliance in the future.
\item HP packets can preempt other types of packets ``on-the-fly''.
\end{itemize}
\end{frame}
\begin{frame}{The WR protocol}
% it's completely transparent
\begin{block}{Preemption mechanism}
When a HP packet arrives at the switch, SP packet currently being routed is terminated so the HP packet can be sent out with minimal latency.
The remaining part of terminated SP packet is sent later.
\end{block}
\begin{center}
\includegraphics[height=4cm]{../pictures/preemption.pdf}
\end{center}
\end{frame}
\subsection{Work so far}
\begin{frame}{Simulation results}{High throughput and determinism achieved simultaneously}
\begin{center}
\includegraphics[height=6.5cm]{../pictures/hostB.pdf}
\end{center}
\end{frame}
\begin{frame}{Switch design}
\begin{center}
\includegraphics[height=6.5cm]{../pictures/switch.pdf}
\end{center}
\end{frame}
\begin{frame}{The switch prototype}{Proof of concept design}
\begin{center}
\includegraphics[width=\columnwidth]{../pictures/switch.jpg}
\end{center}
\end{frame}
\begin{frame}{Tests}{80 ps accuracy over 5km fiber link}
\begin{center}
\includegraphics[height=6.5cm]{../pictures/plot_hist.pdf}
\end{center}
\end{frame}
%\subsection*{Part 2 Summary}
\begin{frame}{Part 2 Summary}
% Keep the summary *very short*.
\begin{itemize}
\item
A data link fulfilling all our needs in \textbf{synchronization} and \textbf{}{determinism}.
\item
Fully based on \textbf{standards} like Synchronous Ethernet and PTP.
\item
A successful \textbf{collaboration} including institutes and companies.
\end{itemize}
% The following outlook is optional.
\vskip0pt plus.5fill
\begin{itemize}
\item
Outlook
\begin{itemize}
\item
Establish a community of developers.
\item
Deliver working prototypes by the end of 2010.
\end{itemize}
\end{itemize}
\end{frame}
\section{Open Hardware}
\begin{frame}{Open Hardware: our definition}
\begin{block}{Publish everything needed to review}
Specifications, discussions, schematics and layouts in some human-readable format, HDL, etc. Publish universally, no NDAs.
\end{block}
%\vspace{0.1cm}
\begin{block}{Publish everything needed to modify}
Schematics and PCB layout files for your favorite EDA tool. Unfortunately the best ones are neither free nor free\ldots
\end{block}
\begin{block}{Publish everything needed to produce}
Manufacturing files, bill of materials, etc.
\end{block}
\end{frame}
\begin{frame}{Advantages}
\begin{block}{Peer review}
Get your design reviewed by experts all around the world, including companies!
\end{block}
%\vspace{0.1cm}
\begin{block}{Design re-use}
How many people are designing a 100 MS/s ADC independently, making the same -- or different -- mistakes?
\end{block}
\begin{block}{Healthier relationship with companies}
No vendor-locked situations. Companies selected solely on the basis of technical excellence, good support and price.
\end{block}
\end{frame}
\begin{frame}{Getting organized}
\begin{block}{\emph{``It's all about interfaces'', Bob Dalesio}}
Your piece of HW can speak to others if you can agree on a set of interfaces. Examples (currently in OHR) include Ethernet, VME, PCIe, FMC\ldots
\end{block}
%\vspace{0.1cm}
\begin{block}{Design compromises}
The price to pay for sharing (and saving time and money) is to choose sub-optimal technical solutions from time to time. We did not choose to write an OS more suited to our needs than Linux, did we?
\end{block}
\end{frame}
%\subsection{Business models}
\begin{frame}{Role of companies}
\begin{block}{Design partners}
Pay a company specialized in a given topic to design a specific card with/for you.
\end{block}
%\vspace{0.1cm}
\begin{block}{Commercial partners}
Buy the cards you designed from a company that will take the charge of manufacturing, testing, managing stocks and providing support.
\end{block}
\end{frame}
\begin{frame}{Some business model examples for commercial partners}
\begin{block}{IBM-style}
Become part of a larger OH team, fully respecting OH practice. Sell full systems based on OH kit.
\end{block}
%\vspace{0.1cm}
\begin{block}{Red Hat-style (kind of)}
Sell manufacture, test and support of individual boards along with a guarantee. Participate in design if needed.
\end{block}
%\vspace{0.1cm}
\begin{block}{Oracle-style}
Support OH kit and build a closed solution on top with added value.
\end{block}
\end{frame}
%\subsection{Legal issues}
\begin{frame}{Licensing}{A quick landscape tour}
\begin{block}{Hardware is not like software}
\begin{itemize}
\item Copyright protects the expression of an idea, not the idea itself.
\item For a schematic (and even HDL), GPL is easily bypassed.
\end{itemize}
\end{block}
%\vspace{0.1cm}
\begin{block}{Options}
\begin{itemize}
\item \href{http://www.tapr.org/ohl.html}{OHL} (viral). If you take my design and use it, you promise not to sue me for patent infringement.
\item \href{http://www.balloonboard.org/docs/Balloon_License_0v2.pdf}{BOHL} (viral). Design files are not released.
\item \href{http://www.opensource.org/licenses/mit-license.php}{MIT}/\href{http://www.linfo.org/bsdlicense.html}{BSD} (non-viral). Do what you like, don't blame me in case of problems.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Licensing}{Our thoughts so far}
\begin{block}{LGPL for HDL}
\begin{itemize}
\item It's very easy to turn a ``used in'' into a ``connected to'' situation in HDL, so GPL would not help.
\item We do want to be informed and profit if our cores are improved.
\end{itemize}
\end{block}
%\vspace{0.1cm}
\begin{block}{MIT/BSD-style for the rest}
\begin{itemize}
\item Not clear how OHL, BOHL and others would perform in court. And don't want to find out!
\item Viral licenses scare some of our potential commercial partners. Could do more harm than good.
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{What about free riders?}
\begin{block}{Free riders are fine}
People and companies who take open designs and do not contribute anything back do not pose a problem to us.
\end{block}
%\vspace{0.1cm}
\begin{block}{But what about \emph{mean} free riders?}
If somebody takes OH and uses it to build a closed solution for a profit, that is fine as well, but we would not be clients.
\end{block}
\end{frame}
\begin{frame}{Mad patent disease and patent trolls}{See \href{http://www.eetimes.com/showArticle.jhtml;?articleID=216600017}{http://www.eetimes.com/showArticle.jhtml;?articleID=216600017}}
\emph{``In this climate, many fear being charged with willfully infringing patents or omitting prior art in patent applications, a charge known as inequitable conduct. So Intel and other companies have put strict procedures in place to control which patents its engineers can read.''}\\
\vspace{0.2cm}
Opening up your designs does make you more vulnerable to this disease.
\end{frame}
%One slide to justify our license choice so far
% One slide on evil patents and the risk for open design.
%\subsection{The Open Hardware Repository}
\begin{frame}{Open Hardware Repository: \href{http://www.ohwr.org}{http://www.ohwr.org}}
\begin{block}{A very useful tool}
A web-based collaborative tool for electronics designers.
\end{block}
%\vspace{0.1cm}
\begin{block}{Made itself of open software}
\begin{itemize}
\item Redmine for wiki and task/issue management.
\item Sympa mailing list manager.
\item SVN/GIT for version management (integrated in Redmine).
\end{itemize}
\end{block}
\begin{block}{Other possible uses}
\begin{itemize}
\item Traceability for Technology Transfer departments.
\item Prove prior art with UTC time stamps in SVN, GIT, wiki...
\end{itemize}
\end{block}
\end{frame}
\begin{frame}{Conclusions}
\begin{block}{Open Hardware looks like a good idea so far}
\begin{itemize}
\item
We can get the best of the custom and COTS worlds.
\item
We are learning a lot, even electronics! ;)
\item
Definitely more fun than closed HW.
\end{itemize}
\end{block}
\begin{block}{Some things not completely clear yet}
\begin{itemize}
\item
Legal framework, work in progress with CERN's KTT group.
\item
We still need a clear collaboration model with companies.
\end{itemize}
\end{block}
First HW due end of 2010, stay tuned!
\end{frame}
\end{document}
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