Point to new document containing a proposal to trigger discussion about using GPL/LGPL for gateware.

Home.md

@@ -150,17 +150,11 @@ CERN uses the following licences for most Open Hardware designs:
     ASICs (VHDL, Verilog, ...)
       - [Example of use in an OHR
         project](https://www.ohwr.org/project/wr-cores/commits/master/modules/timing/dmtd_with_deglitcher.vhd)
-      - Note: for gateware there is currently no proper copyleft
-        license. We hope one day that the CERN OHL will evolve to cover
-        HDL designs adequately \[1\]. In the meantime we are using LGPL
-        (a license which was never intended for gateware) as many other
-        people do, including many projects in opencores.org.
-          - \[1\] In fact, we will start working on a new version of the
-            CERN OHL soon, with exactly that aim. You can find some
-            preliminary thoughts at
-            http://lists.ohwr.org/sympa/arc/cernohl/2013-07/msg00029.html
-            (you might have to click on "I'm not a spammer" and paste
-            the URL again afterwards)
+      - Note: we think that there is curently no perfect copyleft
+        license for gateware. We are trying to contribute to remedy that
+        situation. See [Document](/project/ohr-meta/wikis/Documents/GPL/LGPL-for-HDL:-open-questions). In the meantime we are using LGPL
+        as many other people do, including many projects in
+        opencores.org.
 
 ### Images