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nanoFIP - Gateware
Commit c0ef0386 authored by egousiou's avatar egousiou
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wf_rx: renamed to wf_rx_deserializer.vhd 

wf_tx: renamed to wf_tx_serializer
wf_deglitcher: renamed to wf_rx_deglitcher
wf_cons_bytes_from_rx: renamed to wf_cons_bytes_processor
wf_slone_bytes_to_DATO renamed to: wf_bytes_to_dato
wf_prod_bytes_to_tx renamed to: wf_prod_bytes_retriever
wf_slone_prod_DATI_bytes_sampler renamed to wf_prod_bytes_to_dati
new nanoFIP outputs added: u_cacer, u_pacer, r_tler, r_fcser; fx_rxd, fx_rxa, fx_txd renamed to fd_rxd, fd_rxcdn, fd_txd; pdc file updated as well.
no broadcast vars in slone mode finally!
broadcast var 91h instead of 04h.
wf_crc: timing for checking the crc bytes changed (before there was no check with respect to the FES)
wf_engine_control: removed the check of # bytes in slone mode; if > 2 data bytes arrive, nanoFIP puts to DATO the first 2.
new units wf_production and wf_consumption created to clearify the structure!


git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@103 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -31,25 +31,25 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
--
--
--! @brief Instantiation of a template RAM4K9 component with
--! word width: 8 bits (1 byte) and
--! memory depth: 512 bytes.
--! @brief Instantiation of a template RAM4K9 memory component with
--! word width : 8 bits and
--! depth : 512 bytes.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 16/08/2010
--! @date 15/12/2010
--
--
--! @version v0.1
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! no dependancies \n
--! ProASIC3 lib \n
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
......@@ -57,14 +57,14 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> pepeline not used! data appears in output 1 clock cycle after the address is given
--! (otherwise it was 2 clock cycles later) slack checked and is ok!
--! -> code cleaned-up and commented \n
--! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
--! address is given (otherwise it was 2 clock cycles later) slack
--! checked and is ok! code cleaned-up and commented \n
--! ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! -> explanation on blka, blkb \n
--
---------------------------------------------------------------------------------------------------
......@@ -91,6 +91,7 @@ entity DualClkRAM is
-- Reset
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
......@@ -107,33 +108,33 @@ entity DualClkRAM is
architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
-- !@brief component RAM4K9:
-- !@brief component RAM4K9 :
--! General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
--! pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9.
--! Both ports are capable of reading and writing, making it possible to write with both ports or
--! read with both ports simultaneously. Moreover, reading from one port while writing to the other
--! is possible.
--! WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1:
--! WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1 :
--! Apect ratio configuration.
--! WENA, WENB
--! WENA, WENB :
--! Switching between Read and Write modes for the respective ports.
--! A Low indicates Write operation and a High indicates a Read.
--! BLKA, BLKB: *******************************************************************
--! These signals are active low and will enable the respective ports when asserted.
--! When BLK signals are de-asserted the output holds the previous value.
--! BLKA, BLKB :
--! Activw low enable for the respective ports.
--! PIPEA, PIPEB
--! PIPEA, PIPEB :
--! Control of the optional pipeline stages.
--! A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output
--! in the same clock cycle.
--! A High indicates a pipelined Read and data appears on the output in the next clock cycle.
--! WMODEA, WMODEB
--! WMODEA, WMODEB :
--! Configuration of the behavior of the output when the RAM is in the Write mode.
--! A Low on this signal makes the output retain data from the previous Read.
--! A Low on this signal makes the output retain data from the previous Read. A High indicates a
--! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
......@@ -153,7 +154,7 @@ architecture RAM4K9 of DualClkRAM is
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
RESET : in std_logic:= 'U';
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
......@@ -164,14 +165,14 @@ architecture RAM4K9 of DualClkRAM is
--!@brief Instantiation of the component VCC
component VCC
port( Y : out std_logic);
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component GND
component GND
port( Y : out std_logic);
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
......@@ -182,19 +183,19 @@ architecture RAM4K9 of DualClkRAM is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
---------------------------------------------------------------------------------------------------
--!@brief: Instantiation of the component RAM4K9.
--! The following configuration has been applied:
--! aspect ratio: 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 to VCC)
--! word width: 8 bits (1 byte); DINA8, DINB8: GND, DOUTA8, DOUTB8: open
--! memory depth: 512 bytes; ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND
--! BLKA, BLKB: GND
--! PIPEA, PIPEB: VCC (pipelined read; data appears on the output in the next clock cycle)
--! WMODEA, WMODEB: GND (in the write mode the output retains the data from the previous read)
--! aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
--! word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open)
--! memory depth : 512 bytes (ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
--! BLKA, BLKB : GND
--! PIPEA, PIPEB : GND (not pipelined read)
--! WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
......@@ -232,7 +233,7 @@ architecture RAM4K9 of DualClkRAM is
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,--POWER,
PIPEA => GROUND,
WMODEA => GROUND,
-- INPUTS concerning port B
......@@ -267,7 +268,7 @@ architecture RAM4K9 of DualClkRAM is
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,--POWER,
PIPEB => GROUND,
WMODEB => GROUND,
-- reset
......
NanoFip.pdc
View file @ c0ef0386
......@@ -333,19 +333,19 @@ set_io fd_wdgn_i \
-DIRECTION Input
set_io fx_rxa_i \
set_io fd_rxcdn_i \
-pinname 121 \
-fixed yes \
-DIRECTION Input
set_io fx_rxd_i \
set_io fd_rxd_i \
-pinname 127 \
-fixed yes \
-DIRECTION Input
set_io fx_txd_o \
set_io fd_txd_o \
-pinname 131 \
-fixed yes \
-DIRECTION Output
......@@ -554,8 +554,25 @@ set_io we_i \
-fixed yes \
-DIRECTION Input
set_io u_cacer_o \
-pinname 78 \
-fixed yes \
-DIRECTION Output
set_io u_pacer_o \
-pinname 79 \
-fixed yes \
-DIRECTION Output
set_io r_tler_o \
-pinname 80 \
-fixed yes \
-DIRECTION Output
set_io r_fcser_o \
-pinname 85 \
-fixed yes \
-DIRECTION Output
#
# Non IO constraints
#
......
nanofip.vhd
View file @ c0ef0386
This diff is collapsed.
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -30,16 +30,17 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! The component DualClkRam (512 bytes) is triplicated; each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter.
--! The memory is dual port; port A is used for reading only, port B for writing only.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/2010
--! @date 10/12/2010
--
--
--! @version v0.1
--! @version v0.02
--
--
--! @details\n
......@@ -54,7 +55,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> code cleaned-up and commented
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -62,6 +63,12 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
......@@ -69,19 +76,19 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
C_RAM_ADDR_LGTH : integer); -- memory depth
c_RAM_ADDR_LGTH : integer); -- memory depth
port (
clk_A_i : in std_logic;
addr_A_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_B_i : in std_logic;
addr_B_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_B_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_B_i : in std_logic;
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_portb_i : in std_logic;
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
......@@ -127,7 +134,7 @@ begin
zero <= '0';
one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_B_i;
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
......@@ -140,14 +147,14 @@ G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
port map ( DINA => s_zeros,
ADDRA => addr_A_i,
ADDRA => addr_porta_i,
RWA => one,
CLKA => clk_A_i,
CLKA => clk_porta_i,
DINB => data_B_i,
ADDRB => addr_B_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_B_i,
CLKB => clk_portb_i,
RESETn => one,
......@@ -161,7 +168,7 @@ end generate;
--! output of the majority voter. The majority voter considers the outputs of the three memories
--! and "calculates" their majority with combinatorial logic.
majority_voter: data_A_o <= (data_o_A_array(0) and data_o_A_array(1)) or
majority_voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
......
wf_VAR_RDY_generator.vhd
View file @ c0ef0386
This diff is collapsed.
wf_bits_to_txd.vhd
View file @ c0ef0386
This diff is collapsed.
wf_slone_bytes_to_DATO.vhd → wf_cons_bytes_to_dato.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_bytes_to_DATO.vhd |
--! @file wf_cons_bytes_to_dato.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -18,27 +18,28 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_slone_bytes_to_DATO --
-- wf_cons_bytes_to_dato --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, the unit is responsible for transering the two desirialized
--! bytes from the filedbus to the 2bytes long bus DAT_O. The bytes are put in the bus
--! one by one as they arrive.
--! @brief In stand-alone mode, if a consumed or consumed broadcast variable has been received,
--! the unit is responsible for transering the two desirialized data-bytes from the
--! filedbus to the 2-bytes long bus DAT_O. The bytes are put in the bus one by one as
--! they arrive, as signal transfer_byte_p_i indicates.
--! Note: After the reception of a correct FCS and the FES the signal VAR1_RDY/ VAR2_RDY
--! is asserted and that signals the user that the data in DAT_O are valid and stable.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/01/2011
--
--
--! @version v0.02
......@@ -46,7 +47,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! wf_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -55,6 +58,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 10/1/2011 v0.02 EG unit renamed from wf_slone_cons_bytes_to_dato to
--! wf_cons_bytes_to_dato; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -63,78 +69,81 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_slone_bytes_to_DATO
--! Entity declaration for wf_cons_bytes_to_dato
--=================================================================================================
entity WF_slone_bytes_to_DATO is
entity wf_cons_bytes_to_dato is
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from WF_cons_bytes_from_rx
transfer_byte_p_i: in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_o(7:0)
--! 10: byte_i transfered to DAT_o(15:8)
-- Signals from the wf_cons_bytes_processor
transfer_byte_p_i : in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_O(7:0)
--! 10: byte_i transfered to DAT_O(15:8)
-- Signals for the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! byte received from the rx unit
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
-- OUTPUTS
-- Signal to WF_prod_bytes_to_tx
-- Signal to the wf_prod_bytes_retriever
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity WF_slone_bytes_to_DATO;
end entity wf_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_slone_bytes_to_DATO is
architecture rtl of wf_cons_bytes_to_dato is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, accrording to the signal
--! transfer_byte_p_i, the first or second byte of the user interface bus DAT_o takes the
--! transfer_byte_p_i, the first or second byte of the user interface bus DAT_O takes the
--! incoming byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
else
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
end if;
end if;
end if;
end process;
end process;
end architecture rtl;
......
wf_cons_frame_validator.vhd
View file @ c0ef0386
This diff is collapsed.
wf_consumption.vhd 0 → 100644
View file @ c0ef0386
This diff is collapsed.
wf_crc.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -26,15 +26,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name WF_crc
--
--
--! @brief The unit includes the modules for the generation of the CRC of serialized data,
--! as well as for the verification of an incoming CRC syndrome
--! @brief The unit includes the modules for the generation of the CRC of serial data,
--! as well as for the verification of an incoming CRC syndrome.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/2010
......@@ -48,17 +46,17 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
--! 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! -> 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content \n
--! -> 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented
--! code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -66,23 +64,33 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--!
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
generic(c_GENERATOR_POLY_length : natural);
generic (c_GENERATOR_POLY_length : natural := 16); --! default value
port (
-- INPUTS
-- Inputs from the wf_rx_deserializer/ wf_tx_serializer
uclk_i : in std_logic; --! 40 MHz clock
nFIP_urst_i : in std_logic; --! internal reset
start_CRC_p_i : in std_logic; --! signaling the beginning of the CRC calculation
nfip_urst_i : in std_logic; --! nanoFIP internal reset
start_crc_p_i : in std_logic; --! beginning of the CRC calculation
data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled
data_bit_ready_p_i : in std_logic; --! indicator of sampling time for data_bit_i
-- OUTPUTS
CRC_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
-- Signal to the wf_rx_deserializer
crc_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
-- Signal to the wf_tx_serializer
crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
);
end entity WF_crc;
......@@ -102,38 +110,41 @@ signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length
begin
---------------------------------------------------------------------------------------------------
--!@brief The gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
gen_16_bit_Register_and_Interconnections: for I in 0 to c_GENERATOR_POLY'left generate
Gen_16_bit_Register_and_Interconnections:
for I in 0 to c_GENERATOR_POLY'left generate
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
iterations: if I > 0 generate
next_iterations: if I > 0 generate
s_q_nx(I) <= s_q(I-1) xor (c_GENERATOR_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process CRC_calculation: the process "moves" the shift register described
--! above, for the calculation of the CRC
CRC_calculation: process(uclk_i)
CRC_calculation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to annex A)
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_q <= (others => '0');
else
if start_CRC_p_i = '1' then
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to the Annex)
elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
......@@ -146,27 +157,27 @@ begin
end process;
-- -- -- -- --
CRC_o <= not s_q;
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data maches the
--! c_VERIFICATION_MASK, it means a correct CRC word has been received and the signal CRC_ok_p
--! gives a pulse.
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data matches the
--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received and the signal
--! crc_ok_p gives a pulse.
Syndrome_Verification: process(s_q, s_crc_bit_ready_p)
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
begin
s_q_check_mask <= s_q xor c_VERIFICATION_MASK;
if (unsigned(not s_q_check_mask)) = 0 then
CRC_ok_p <= s_crc_bit_ready_p;
crc_ok_p <= s_crc_bit_ready_p;
else
CRC_ok_p <= '0';
crc_ok_p <= '0';
end if;
end process;
......
wf_decr_counter.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
---------------------------------------------------------------------------------------------------
......@@ -13,22 +21,21 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
-- WF_decr_counter --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Synchronous decreasing counter with a load enable and decrease enable signals;
--! @brief Synchronous decreasing counter with a reset, a load enable & a decrease
--! enable signal.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 10/2010
--
--
--! @version v0.02
--! @version v0.01
--
--
--! @details \n
......@@ -37,7 +44,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -50,30 +56,36 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_decr_counter
--=================================================================================================
entity WF_decr_counter is
generic(counter_length : natural);
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
counter_top : in unsigned (counter_length-1 downto 0); --! load value
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
counter_load_i : in std_logic; --! load enable
counter_decr_p_i : in std_logic; --! decrement enable
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (counter_length-1 downto 0);--! counter
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_zero_o : out std_logic --! empty counter indication
);
end entity WF_decr_counter;
......@@ -84,18 +96,20 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned(counter_length-1 downto 0);
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
Decr_Counter: process(uclk_i)
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_counter <= (others => '0');
else
......@@ -110,8 +124,8 @@ signal s_counter : unsigned(counter_length-1 downto 0);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
......
wf_engine_control.vhd
View file @ c0ef0386
This diff is collapsed.
wf_incr_counter.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -24,17 +24,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief Fully synchronous increasing counter with a reset, a reinitialise & an enable signal
--! @brief Synchronous increasing counter with a reset, a reinitialise and an increase
--! enable signal.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 10/2010
--
--
--! @version v0.02
--! @version v0.01
--
--
--! @details \n
......@@ -43,7 +44,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -62,24 +62,25 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity WF_incr_counter is
generic(counter_length : natural);
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i: in std_logic; --! increment enable
incr_counter_i : in std_logic; --! increment enable
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned(counter_length-1 downto 0); --! counter
counter_is_full_o : out std_logic --! all counter bits at '1'
);
counter_o : out unsigned(g_counter_lgth-1 downto 0); --! counter
counter_is_full_o : out std_logic --! counter full indication
); --! (all bits to '1')
end entity WF_incr_counter;
......@@ -88,20 +89,23 @@ end entity WF_incr_counter;
--=================================================================================================
architecture rtl of WF_incr_counter is
signal s_counter, s_counter_full : unsigned(counter_length-1 downto 0);
signal c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0);
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
c_COUNTER_FULL <= (others => '1');
s_counter_full <= (others => '1');
---------------------------------------------------------------------------------------------------
Incr_Counter: process(uclk_i)
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if nfip_urst_i = '1' then
s_counter <= (others => '0');
elsif reinit_counter_i = '1' then
......@@ -114,9 +118,10 @@ signal s_counter, s_counter_full : unsigned(counter_length-1 downto 0);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter= s_counter_full
else '0';
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
......
wf_inputs_synchronizer.vhd
View file @ c0ef0386
This diff is collapsed.
wf_manch_code_viol_check.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
--! @file WF_manch_code_viol_check.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -27,10 +27,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit follows an incoming serial signal and outputs a pulse
--! if a manchester 2 code violation is detected.
--! It is assumed that a violation happens if after half reception period
--! plus 2 uclck periods, the incoming signal has not had a transition.
--! @brief The unit follows the incoming deglitched serial signal and outputs a pulse if a
--! Manchester 2 (manch.) code violation is detected.
--! It is assumed that a violation happens if after a half-bit-clock period (plus 2 uclk
--! periods), the incoming signal has not had a transition.
--! Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
--! should be sampled (before and after a significant edge), whereas the
--! sample_bit_p includes only the sampling of the 1st part, before the transition.
--! Example:
--! bit : 0
--! manch. encoded : _|-
--! sample_manch_bit_p : ^ ^
--! sample_bit_p : ^ (this sampling will give the 0)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -54,6 +63,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/12/2010 v0.02 EG cleaning-up+commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -70,20 +80,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity WF_manch_code_viol_check is
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from WF_rx
-- Signals from the wf_rx_deserializer
serial_input_signal_i : in std_logic; --! input signal
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
-- OUTPUTS
-- Signal to WF_rx
-- Signal to the wf_rx_deserializer
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
);
end entity WF_manch_code_viol_check;
......@@ -99,32 +109,29 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Check_Code_Violations:in order to check the existance code violations
--! the input signal is delayed by half reception period.
--! The signal check_code_viol_p is a pulse with period the reception period. The pulse occurs
--! 2 uclk periods after a manch. transition is expected.
--!@brief Synchronous process Check_Code_Violations: in order to check for code violations, the
--! input signal is delayed by half-bit-clock period (serial_input_signal_d).
--! The signal check_code_viol_p is a pulse occuring 2 uclk periods after a manch. transition is
--! expected.
--! As the following drawing roughly indicates, a violation exists if the signal and its delayed
--! version are identical on the s_check_code_viol_p moments.
--! version are identical on the check_code_viol_p moments.
-- 0 V- 1
-- rxd_filtered_o: __|--|____|--|__
-- s_serial_input_signal_d: __|--|____|--|__
-- s_check_code_viol_p: ^ ^ ^
-- rxd_filtered : __|--|____|--|__
-- serial_input_signal_d : __|--|____|--|__
-- check_code_viol : ^ ^ ^
Check_code_violations: process(uclk_i)
Check_code_violations: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nFIP_urst_i = '1' then
s_check_code_viol_p <='0';
s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0';
s_serial_input_signal_d <='0';
if nfip_urst_i = '1' then
s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_serial_input_signal_d <= '0';
else
......@@ -132,7 +139,7 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
s_serial_input_signal_d <= serial_input_signal_i;
end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- small delay
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
end if;
......@@ -140,6 +147,7 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment
manch_code_viol_p_o <= s_check_code_viol_p and
(not (serial_input_signal_i xor s_serial_input_signal_d));
......
wf_manch_encoder.vhd
View file @ c0ef0386
--=================================================================================================
--! @file wf_manch_encoder.vhd
--=================================================================================================
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_manch_encoder.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -9,26 +17,25 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- wf_manch_encoder --
-- --
-- CERN, BE/CO/HT --
-- WF_manch_encoder --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief
--! @brief Encoding of a word to its Manchester 2 (manch.) equivalent.
--! This code ensures that there is one transition for each bit.
--! bit : "0" "1"
--! manch. encoded : "0 1" "1 0"
--! scheme : _|- -|_
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/12/2010
--
--
--! @version v0.02
......@@ -39,12 +46,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG 1st version \n
--! -> 12/2010 v0.02 EG cleaned-up, commented \n
--!
--
---------------------------------------------------------------------------------------------------
--
......@@ -53,21 +63,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_manch_encoder
--=================================================================================================
entity wf_manch_encoder is
generic(word_length : natural);
generic (word_length : natural := 8); --! default length: 8
port (
-- INPUT
word_i : in std_logic_vector(word_length-1 downto 0);
word_i : in std_logic_vector(word_length-1 downto 0); --! input word
-- OUTPUT
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0) --! output encoded word
);
end entity wf_manch_encoder;
......@@ -81,18 +96,22 @@ architecture rtl of wf_manch_encoder is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--! @brief combinatorial process Manchester_Encoder_byte: The process takes a byte (8 bits) and
--! creates its manchester encoded equivalent (16 bits). Each bit '1' is replaced by '10' and each
--! bit '0' by '01'.
--! @brief Combinatorial process Manchester_Encoder: The process takes a word (ex. 8 bits) and
--! creates its manchester encoded equivalent (ex. 16 bits).
--! Each bit '1' is replaced by '10' and each bit '0' by '01'.
Manchester_Encoder_byte: process(word_i)
Manchester_Encoder: process (word_i)
begin
for I in word_i'range loop
word_manch_o(I*2) <= not word_i(I);
word_manch_o(I*2+1) <= word_i(I);
end loop;
end process;
......
wf_model_constr_decoder.vhd
View file @ c0ef0386
This diff is collapsed.
wf_package.vhd
View file @ c0ef0386
This diff is collapsed.
wf_slone_DATI_bytes_sampler.vhd → wf_prod_bytes_to_dati.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_DATI_bytes_sampler.vhd
--! @file wf_prod_bytes_from_dati.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,27 +18,25 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_slone_DATI_bytes_sampler --
-- --
-- CERN, BE/CO/HT --
-- wf_prod_bytes_from_dati --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Unit responsible for the sampling of the DAT_I bus for the stand-alone operation.
--! Following to the functional specs page 14, in stand-alone mode, nanoFIP samples the
--! data onthe first clock cycle after the deassertion of VAR3_RDY.
--! @brief Unit responsible for the sampling of the DAT_I bus in stand-alone operation.
--! Following to the functional specs page 15, in stand-alone mode, the nanoFIP
--! samples the data on the first clock cycle after the deassertion of VAR3_RDY.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 04/01/2011
--
--
--! @version v0.02
......@@ -39,6 +45,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -47,6 +55,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! wf_prod_bytes_from_dati; cleaning-up + commenting
--!
--
---------------------------------------------------------------------------------------------------
--
......@@ -55,42 +67,47 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_slone_DATI_bytes_sampler
--! Entity declaration for wf_prod_bytes_from_dati
--=================================================================================================
entity WF_slone_DATI_bytes_sampler is
entity wf_prod_bytes_from_dati is
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (triply buffered with uclk)
-- Signals from WF_engine_control
var3_rdy_i : in std_logic;
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronised with uclk)
-- Signals from the WF_engine_control
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- includes RP_DAT.Control and RP_DAT.Data
-- OUTPUTS
-- Signal to WF_prod_bytes_to_tx
slone_byte_o : out std_logic_vector (7 downto 0)
-- OUTPUTS
-- Signal to the wf_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! byte to be sent
);
end entity WF_slone_DATI_bytes_sampler;
end entity wf_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_slone_DATI_bytes_sampler is
architecture rtl of wf_prod_bytes_from_dati is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
......@@ -98,27 +115,29 @@ architecture rtl of WF_slone_DATI_bytes_sampler is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Sample_Data_i: the sampling of DAT_I has to take place on the first
--! clock cycle after the deassettion of VAR3_RDY.
-- Since slone_data_i is the triply buffered version of the input bus DAT_I, the signal VAR3_RDY
-- has to be delayed too.
--!@brief Synchronous process Sample_DAT_I_bus: the sampling of the DAT_I bus in stand-alone mode
--! has to take place on the first clock cycle after the de-assertion of VAR3_RDY.
--! Note: Since slone_data_i is the triply buffered version of the bus DAT_I (for synchronisation),
--! the signal VAR3_RDY has to be (internally) delayed for 3 uclk cycles too, before the sampling;
--! the 4th delay is added in order to achieve the sampling 1 uclk AFTER the de-assertion.
Sample_Data_i: process(uclk_i)
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
s_var3_rdy_d4 <= s_var3_rdy_d4(2 downto 0) & var3_rdy_i;
if s_var3_rdy_d4(3) = '1' then -- data latching
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end process;
......
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wf_reset_unit.vhd
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......@@ -10,7 +10,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
......@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
......@@ -40,12 +40,12 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_cons_bytes_from_rx\n
--! \n<b>Dependencies:</b> \n
--! wf_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
......@@ -69,7 +69,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity WF_reset_unit is
port (
-- INPUTS
-- User Interface general signals (synchronized) (after synchronization)
-- nanoFIP User Interface, General signals (synchronized with uclk) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
......@@ -77,7 +77,7 @@ entity WF_reset_unit is
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type
var_i : in t_var; --! variable type that is being treated
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
......@@ -86,10 +86,10 @@ entity WF_reset_unit is
-- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface
-- nanoFIP User Interface output
rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
);
end entity WF_reset_unit;
......@@ -108,7 +108,7 @@ architecture rtl of WF_reset_unit is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the (buffered) input signal rstin
......@@ -117,7 +117,7 @@ architecture rtl of WF_reset_unit is
s_rst_creation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if (urst_i = '1') then -- when the rstin in ON
if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 16 (then stays at 16)
......@@ -153,13 +153,13 @@ end process;
--! is received and the 1st byte contains the station address.
--!The signal reset_nFIP_and_FD stays asserted until the end of the transmission of the RP_DAT frame
--! fd_rstn_o: fieldrive reset, active low; active when a reset variable is received and the 1st
--! fd_rstn_o: FIELDRIVE reset, active low; active when a reset variable is received and the 1st
--! byte contains the station address.
--! The signal reset_nFIP_and_FD_i stays asserted until a new variable for this station is received
Reset_Outputs: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
rston_o <= not assert_RSTON_p_i;
nFIP_rst_o <= s_rst or rst_nFIP_and_FD_p_i;
......
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wf_status_bytes_gen.vhd
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