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nanoFIP - Gateware
Commit 40153778 authored by egousiou's avatar egousiou
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"cosmetics" in package+engine 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@105 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 3c37fd5f
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nanofip.vhd
View file @ 40153778
......@@ -252,14 +252,14 @@ begin
rx_FSS_received_p_i => s_cons_fss_decoded_p,
rx_byte_ready_p_i => s_cons_byte_ready_p,
rx_byte_i => s_cons_byte,
rx_CRC_FES_ok_p_i => s_fss_crc_fes_viol_ok_p,
produce_wait_turnar_time => s_fss_crc_fes_viol_ok_p,
rx_crc_wrong_p_i => s_cons_crc_wrong_p,
tx_sending_mps_i => s_prod_sending_mps,
rx_ctrl_byte_i => s_cons_ctrl_byte,
rx_pdu_byte_i => s_cons_PDU_byte,
rx_length_byte_i => s_cons_lgth_byte,
rx_var_rst_byte_1_i => s_cons_var_rst_byte_1,
rx_var_rst_byte_2_i => s_cons_var_rst_byte_2,
prod_sending_mps_i => s_prod_sending_mps,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_PDU_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
rate_i => s_rate_synch,----------------
subs_i => s_subs_synch,----------------
p3_lgth_i => s_p3_lgth_synch, ----------------------
......@@ -269,12 +269,12 @@ begin
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_prod_p ,
tx_start_prod_p_o => s_start_prod_p ,
tx_byte_ready_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
tx_rx_byte_index_o => s_cons_prod_byte_index_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_ready_from_control,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
cons_byte_ready_p_o => s_cons_byte_ready_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
......
wf_VAR_RDY_generator.vhd
View file @ 40153778
......@@ -86,31 +86,31 @@ entity WF_var_rdy_generator is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct consumed frame
var_i : in t_var; --! variable type that is being treated
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
var_i : in t_var; --! variable type that is being treated
-- Signals from the wf_cons_bytes_processor
rx_var_rst_byte_1_i : in std_logic_vector(7 downto 0); --! first & second data bytes of a
rx_var_rst_byte_2_i : in std_logic_vector(7 downto 0); --! reset variable
cons_var_rst_byte_1_i : in std_logic_vector(7 downto 0);--! first & second data bytes of a
cons_var_rst_byte_2_i : in std_logic_vector(7 downto 0);--! reset variable
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
-- Signals for the WF_reset_unit
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
);
end entity WF_var_rdy_generator;
......@@ -275,12 +275,12 @@ begin
if var_i = var_rst then
if rx_var_rst_byte_1_i = subs_i then
if cons_var_rst_byte_1_i = subs_i then
s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current RP_DAT frame
if rx_var_rst_byte_2_i = subs_i then
if cons_var_rst_byte_2_i = subs_i then
s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current RP_DAT frame
......
wf_cons_bytes_processor.vhd
View file @ 40153778
......@@ -145,7 +145,7 @@ architecture rtl of wf_cons_bytes_processor is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_rx_Length_byte : std_logic_vector (7 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
......@@ -207,14 +207,14 @@ begin
--! In memory mode, the incoming bytes (byte_i) after the Control byte and before the CRC bytes,
--! are written in the memory one by one as they arrive, on the moments when the signal
--! byte_ready_p_i is active.
--! The signals byte_index_i and Length (s_rx_Length_byte) are used to coordinate which bytes are
--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to coordinate which bytes are
--! written and which are not:
--! the Control byte, that arrives when byte_index_i = 0, is not written
--! and the CRC bytes are not written by checking the amount of bytes indicated by the Length byte.
--! The byte_index_i signal is counting each byte after the FSS and before the FES (therefore,
--! apart from all the pure data-bytes,it also includes the Control, PDU, Length, MPS & CRC bytes).
--! The Length byte (s_rx_Length_byte) is received from the wf_rx_deserializer when byte_index_i is equal to 3
--! The Length byte (s_cons_lgth_byte) is received from the wf_rx_deserializer when byte_index_i is equal to 3
--! and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
--! before the CRC.
......@@ -225,7 +225,7 @@ begin
--! If the consumed variable is the reset one the process latches the first and second data bytes.
Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_rx_Length_byte)
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
......@@ -255,7 +255,7 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
if byte_index_i > c_LENGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then -- less or eq
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then -- less or eq
s_write_byte_to_mem_p <= byte_ready_p_i; -- "Length" amount of
-- bytes are written
else
......@@ -305,7 +305,7 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
if byte_index_i > c_LENGTH_BYTE_INDEX then
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then
s_write_byte_to_mem_p <= byte_ready_p_i;
else
......@@ -409,7 +409,7 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
if nfip_urst_i = '1' then
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
s_cons_lgth_byte <= (others => '0');
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only for consumed vars
......@@ -421,20 +421,20 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
cons_pdu_byte_o <= byte_i;
elsif ((byte_index_i = c_LENGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
s_rx_Length_byte <= byte_i;
s_cons_lgth_byte <= byte_i;
end if;
else
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
s_cons_lgth_byte <= (others => '0');
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_rx_Length_byte;
cons_lgth_byte_o <= s_cons_lgth_byte;
end architecture rtl;
--=================================================================================================
......
wf_cons_frame_validator.vhd
View file @ 40153778
......@@ -86,9 +86,9 @@ entity WF_cons_frame_validator is
port (
-- INPUTS
-- Signals from the wf_cons_bytes_processor unit
rx_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signal from the wf_rx_deserializer unit
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC
......@@ -116,7 +116,7 @@ end entity WF_cons_frame_validator;
--=================================================================================================
architecture rtl of WF_cons_frame_validator is
signal s_rx_ctrl_byte_ok, s_rx_pdu_byte_ok, s_rx_length_byte_ok : std_logic;
signal s_cons_ctrl_byte_ok, s_cons_pdu_byte_ok, s_cons_lgth_byte_ok : std_logic;
--=================================================================================================
-- architecture begin
......@@ -126,13 +126,13 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT
--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC, FSS, FES and code violations.
--! The bytes rx_ctrl_byte_i, rx_pdu_byte_i, rx_length_byte_i that arrive at the beginning of a
--! The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that arrive at the beginning of a
--! frame, have been registered and keep their values until the end of a frame.
--! The signal rx_fss_crc_fes_viol_ok_p_i, is a pulse at the end of the FES that combines
--! the check of the FSS, CRC, FES and the code violations.
Consumed_Frame_Validator: process (var_i, rx_ctrl_byte_i, rx_byte_index_i, rx_pdu_byte_i,
rx_fss_crc_fes_viol_ok_p_i, rx_length_byte_i, rx_crc_wrong_p_i)
Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
rx_fss_crc_fes_viol_ok_p_i, cons_lgth_byte_i, rx_crc_wrong_p_i)
begin
case var_i is
......@@ -141,18 +141,18 @@ begin
when var_1 | var_2 | var_rst => -- only for consumed RP_DAT frames
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
if cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_cons_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
s_cons_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_pdu_byte_ok <= '1'; -- PDU_TYPE byte
if cons_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_cons_pdu_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_pdu_byte_ok <= '0' ;
s_cons_pdu_byte_ok <= '0' ;
end if;
......@@ -160,17 +160,17 @@ begin
if rx_fss_crc_fes_viol_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the end of frame
-- arrives correctly.
if rx_byte_index_i = (unsigned(rx_length_byte_i) + 5) then -- rx_byte_index starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from the
if rx_byte_index_i = (unsigned(cons_lgth_byte_i) + 5) then -- rx_byte_index starts counting
s_cons_lgth_byte_ok <= '1'; -- from 0 and apart from the
-- user-data bytes, also counts the
else -- Control, PDU_TYPE, Length,
-- the 2 CRC and the FES bytes
s_rx_length_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
end if;
else
s_rx_length_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
end if;
......@@ -181,17 +181,17 @@ begin
-----------------------------------------------------------------------------------------------
-- when var_presence | var_identif | var_3 | var_whatever =>
-- s_rx_ctrl_byte_ok <= '0';
-- s_rx_pdu_byte_ok <= '0';
-- s_rx_length_byte_ok <= '0';
-- s_cons_ctrl_byte_ok <= '0';
-- s_cons_pdu_byte_ok <= '0';
-- s_cons_lgth_byte_ok <= '0';
-------------------------------------------------------------------------------------------------
when others =>
s_rx_ctrl_byte_ok <= '0';
s_rx_pdu_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
s_cons_ctrl_byte_ok <= '0';
s_cons_pdu_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
nfip_status_r_fcser_p_o <= '0';
end case;
......@@ -201,13 +201,13 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignment for the output signals
cons_frame_ok_p_o <= rx_fss_crc_fes_viol_ok_p_i and
s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
nfip_status_r_tler_o <= s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
nfip_status_r_tler_o <= s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
end architecture rtl;
--=================================================================================================
......
wf_engine_control.vhd
View file @ 40153778
......@@ -56,13 +56,14 @@ use work.WF_PACKAGE.all;
--! \n\n<b>Last changes:</b>\n
--! 07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG E0 added as broadcast \n
--! PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle
--! PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion;
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle;
--! state consume_wait_FSS, for the correct use of the silence time(time
--! stops counting when an RP_DAT frame has started)
--!
--! 12/2010 v0.02 EG removed check on slone mode for #bytes>4
--! 12/2010 v0.02 EG removed check on slone mode for #bytes>4;
--! in slone no broadcast
--! 01/2011 v0.03 EG signals named according to their origin
--
---------------------------------------------------------------------------------------------------
--
......@@ -76,81 +77,86 @@ use work.WF_PACKAGE.all;
--=================================================================================================
entity WF_engine_control is
generic ( c_QUARTZ_PERIOD : real);
generic (c_QUARTZ_PERIOD : real);
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced variable data length
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the wf_tx_serializer unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the wf_rx_deserializer unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected by wf_rx_deserializer
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic; --! indication of a wrong CRC reception
tx_request_byte_p_i : in std_logic; --!
-- Signal from the wf_prod_bytes_retriever
tx_sending_mps_i : in std_logic;
prod_sending_mps_i : in std_logic; --! indication than the MPS byte is being sent
-- Signal from the wf_prod_bytes_retriever
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-- Signals from the wf_rx_deserializer unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected
rx_byte_ready_p_i : in std_logic; --! indication of a new byte on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); --! deserialized byte
rx_crc_fes_viol_ok_p_i : in std_logic; --! indication of a correct CRC and FES reception
rx_crc_wrong_p_i : in std_logic; --! indication of a wrong CRC reception
-- Signal from the wf_cons_bytes_processor
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Control byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0); --! 1st data byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0); --! 2nd data byte of a received var_rst
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE nanoFIP outputs
var1_rdy_o : out std_logic; --! signals new data received and can safely be read
var2_rdy_o : out std_logic; --! signals new data received and can safely be read
var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
var1_rdy_o : out std_logic;--! signals new data is received and can safely be read
var2_rdy_o : out std_logic;--! signals new data is received and can safely be read
var3_rdy_o : out std_logic;--! signals that data can safely be written
-- Signal to the wf_tx_serializer unit
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM
tx_byte_ready_p_o : out std_logic;--!
-- Signal to the wf_rx_deserializer
rst_rx_unit_p_o : out std_logic;--! if an FES has not arrived after 8 bytes of an ID_DAT,
--! or after 134 bytes of an RP_DAT, the state machine
--! of the wf_rx_deserializer unit returns to idle state
rst_rx_unit_p_o : out std_logic;--!if an FES has not arrived after 8 bytes of an ID_DAT
--! or after 134 bytes of an RP_DAT, the state machine
--! of the wf_rx_deserializer unit returns to idle state
-- Signal to the wf_cons_bytes_processor, wf_prod_bytes_retriever, WF_reset_unit, WF_status_bytes_gen,
-- Signal to the wf_cons_bytes_processor, wf_prod_bytes_retriever, wf_reset_unit,
-- wf_var_rdy_generator, wf_prod_data_lgth_calc, wf_cons_frame_validator
var_o : out t_var;
-- Signal to the wf_cons_bytes_processor, wf_prod_bytes_retriever
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
-- Signal to the wf_prod_bytes_retriever
tx_data_length_o : out std_logic_vector (7 downto 0);
prod_data_length_o : out std_logic_vector (7 downto 0); --! # bytes of the Conrol & Data
--! fields of a prod RP_DAT frame
-- Signal to the wf_tx_serializer
tx_byte_ready_p_o : out std_logic;
-- Signal to the wf_cons_bytes_processor
rx_byte_ready_p_o : out std_logic;
cons_byte_ready_p_o : out std_logic;
-- Signal to the WF_reset_unit
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
assert_rston_p_o : out std_logic; --! indicates that a var_rst with its 2nd data-byte
--! containing the station's address has been
--! correctly received
rst_nfip_and_fd_p_o : out std_logic; --! indicates that a var_rst with its 1st data-byte
--! containing the station's address has been
--! correctly received
-- Signal to the WF_status_bytes_gen
nfip_status_r_fcser_p_o : out std_logic; --! indication of a wrong CRC reception
rst_status_bytes_o : out std_logic;
nfip_status_r_tler_o : out std_logic
rst_status_bytes_o : out std_logic; --! resets the nanoFIP and MPS status bytes
nfip_status_r_fcser_p_o : out std_logic; --! nanoFIP status byte, bit 5
nfip_status_r_tler_o : out std_logic --! nanoFIP status byte, bit 4
);
end entity WF_engine_control;
......@@ -163,27 +169,28 @@ end entity WF_engine_control;
architecture rtl of WF_engine_control is
type control_st_t is (idle, id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, consume, consume_wait_FSS,
id_dat_frame_ok, produce_wait_respon_time, cont_w_cons_watchdog, produce);
type control_st_t is (idle, id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte,
id_dat_frame_ok, consume, consume_wait_FSS, produce_wait_turnar_time,
produce);
signal control_st, nx_control_st : control_st_t;
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var, s_var_id : t_var;
signal s_load_var, s_load_var_aux, s_tx_byte_ready_p_d1 : std_logic;
signal s_load_time_c, s_tx_byte_ready_p_d2 : std_logic;
signal s_load_time_counter, s_tx_byte_ready_p_d2 : std_logic;
signal s_tx_start_prod_p : std_logic;
signal s_time_c_is_zero, s_broadcast_var : std_logic;
signal s_inc_rx_bytes_counter, s_tx_last_byte_p :std_logic;
signal s_tx_data_length_match, s_tx_byte_ready_p, s_cons_frame_ok_p :std_logic;
signal s_rx_bytes_c, s_tx_bytes_c : unsigned(7 downto 0);
signal s_tx_data_length : std_logic_vector(7 downto 0);
signal s_prod_data_length_match, s_tx_byte_ready_p, s_cons_frame_ok_p :std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned(7 downto 0);
signal s_prod_data_length : std_logic_vector(7 downto 0);
signal s_time_counter_top, s_time_c: unsigned(14 downto 0);
signal s_turnaround_time, s_silence_time : unsigned(14 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
signal s_id_dat_subs_byte, s_id_dat_frame_ok : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS: std_logic;
signal s_prod_wait_resp_time, s_producing, s_consuming : std_logic;
signal s_prod_wait_turnar_time, s_producing, s_consuming : std_logic;
signal s_rst_tx_bytes_counter, s_inc_tx_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d: std_logic;
signal s_tx_byte_index, s_rx_byte_index : std_logic_vector (7 downto 0);
......@@ -195,6 +202,9 @@ architecture rtl of WF_engine_control is
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- engine_control_FSM --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief central control FSM: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
......@@ -224,7 +234,7 @@ begin
Central_Control_FSM_Comb_State_Transitions:process (control_st, rx_FSS_received_p_i, s_tx_last_byte_p,
s_var_id, rx_byte_ready_p_i,rx_byte_i, s_rx_bytes_c,
s_time_c_is_zero,s_produce_or_consume,subs_i,
rx_CRC_FES_ok_p_i, s_broadcast_var)
rx_crc_fes_viol_ok_p_i, s_broadcast_var)
begin
......@@ -233,7 +243,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle =>
if rx_FSS_received_p_i = '1' then -- notification from the receiver that a correct FSS field has been received
if rx_FSS_received_p_i = '1' then -- correct FSS arrived
nx_control_st <= id_dat_control_byte;
else
......@@ -242,109 +252,110 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_control_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte;
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle;
nx_control_st <= idle; -- byte different than the expected ID_DAT Control
else
nx_control_st <= id_dat_control_byte;
nx_control_st <= id_dat_control_byte;-- byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_var_byte =>
if (rx_byte_ready_p_i = '1') and (s_var_id /= var_whatever) then
nx_control_st <= id_dat_subs_byte;
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle;
nx_control_st <= idle; -- byte not corresponding to an expected variable
else
nx_control_st <= id_dat_var_byte;
nx_control_st <= id_dat_var_byte; -- byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = subs_i) then
nx_control_st <= id_dat_frame_ok;
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then-- at this moment we do not
nx_control_st <= id_dat_frame_ok; -- check if slone=1, as the
-- rst var which is broad-
-- cast is treaded in slone
elsif (rx_byte_ready_p_i = '1') then
elsif (rx_byte_ready_p_i = '1') then -- not the station's address, neither a broadcast
nx_control_st <= idle;
else
nx_control_st <= id_dat_subs_byte;
nx_control_st <= id_dat_subs_byte; -- byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok =>
if (rx_CRC_FES_ok_p_i = '1') and (s_produce_or_consume = "10") then
nx_control_st <= produce_wait_respon_time;
if (rx_crc_fes_viol_ok_p_i = '1') and (s_produce_or_consume = "10") then
nx_control_st <= produce_wait_turnar_time; -- CRC & FES check ok! station has to produce
elsif (rx_CRC_FES_ok_p_i = '1') and (s_produce_or_consume = "01") then
nx_control_st <= consume_wait_FSS;
elsif (rx_crc_fes_viol_ok_p_i = '1') and (s_produce_or_consume = "01") then
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (rx_CRC_FES_ok_p_i = '1') and (s_rx_bytes_c > 2) then
nx_control_st <= idle;
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= idle; -- byte, there has not been detected a FES
-- s_rx_bytes_c: starts counting at this state
else
nx_control_st <= id_dat_frame_ok;
nx_control_st <= id_dat_frame_ok; -- bytes being arriving (CRC & FES)
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce_wait_respon_time =>
when produce_wait_turnar_time =>
if s_time_c_is_zero = '1' then
nx_control_st <= produce;
if s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= produce;
else
nx_control_st <= produce_wait_respon_time;
nx_control_st <= produce_wait_turnar_time;-- waiting for turnaround time to pass
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume_wait_FSS =>
if rx_FSS_received_p_i = '1' then
if rx_FSS_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
nx_control_st <= consume;
elsif s_time_c_is_zero = '1' then -- if no consumed RP_DAT frame arrives after the
nx_control_st <= idle; -- silence time, the engine goes back to idle state
elsif s_time_c_is_zero = '1' then -- if no consumed RP_DAT frame arrives after the
nx_control_st <= idle; -- silence time, the engine goes back to idle
else
nx_control_st <= consume_wait_FSS;
nx_control_st <= consume_wait_FSS; -- counting silence time
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume =>
if (rx_CRC_FES_ok_p_i = '1') or -- if the RP_DAT frame finishes as
(s_rx_bytes_c > 130) then -- expected with a FES,
-- or if no FES has arrived after the max
-- number of bytes expected, the engine
nx_control_st <= idle; -- goes back to idle state.
if (rx_crc_fes_viol_ok_p_i = '1') or -- if the RP_DAT frame finishes as
(s_rx_bytes_c > 130) then -- expected with a FES,
-- or if no FES has arrived after the max
-- number of bytes expected, the engine
nx_control_st <= idle; -- goes back to idle
else
nx_control_st <= consume;
nx_control_st <= consume; -- consuming bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce =>
if s_tx_last_byte_p = '1' then
if s_tx_last_byte_p = '1' then -- last byte to be produced
nx_control_st <= idle;
else
nx_control_st <= produce;
nx_control_st <= produce; -- producing bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -362,141 +373,135 @@ begin
case control_st is
when idle =>
s_idle_state <= '1';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '1';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when id_dat_control_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '1';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '1';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when id_dat_var_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '1';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '1';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when id_dat_subs_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '1';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '1';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when id_dat_frame_ok =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '1';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when produce_wait_respon_time =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '1';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '1';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when produce_wait_turnar_time =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '1';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when consume_wait_FSS =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '1';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '1';
s_consuming <= '0';
s_producing <= '0';
when consume =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '1';
s_producing <= '0';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '1';
s_producing <= '0';
when produce =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '1';
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '1';
when others =>
s_idle_state <= '1';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_resp_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
s_idle_state <= '1';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Validation of a consumed RP_DAT frame (FSS, Control, PDU_TYPE, Length, --
-- CRC, FES, Code Violations) and Generation of the signals --
-- VAR_RDY, R_TLER, R_FCSER --
---------------------------------------------------------------------------------------------------
Prod_Data_Length_Calculator: WF_prod_data_lgth_calc
port map(
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
var_i => s_var,
------------------------------------
tx_data_length_o => s_tx_data_length
------------------------------------
);
tx_data_length_o <= s_tx_data_length;
---------------------------------------------------------------------------------------------------
Cons_Frame_Validator: WF_cons_frame_validator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Consumed_Frame_Validator: WF_cons_frame_validator
port map(
rx_ctrl_byte_i => rx_ctrl_byte_i,
rx_pdu_byte_i => rx_pdu_byte_i,
rx_length_byte_i => rx_length_byte_i,
rx_fss_crc_fes_viol_ok_p_i => rx_CRC_FES_ok_p_i,
cons_ctrl_byte_i => cons_ctrl_byte_i,
cons_pdu_byte_i => cons_pdu_byte_i,
cons_lgth_byte_i => cons_lgth_byte_i,
rx_fss_crc_fes_viol_ok_p_i => rx_crc_fes_viol_ok_p_i,
rx_crc_wrong_p_i => rx_crc_wrong_p_i,
var_i => s_var,
rx_byte_index_i => s_rx_bytes_c,
......@@ -506,62 +511,89 @@ begin
cons_frame_ok_p_o => s_cons_frame_ok_p);
----------------------------------------------------
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VAR_RDY_Signals_Generation: WF_var_rdy_generator
port map (
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nfip_urst_i => nfip_urst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => s_var,
rx_var_rst_byte_1_i => rx_var_rst_byte_1_i,
rx_var_rst_byte_2_i => rx_var_rst_byte_2_i,
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nfip_urst_i => nfip_urst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => s_var,
cons_var_rst_byte_1_i => cons_var_rst_byte_1_i,
cons_var_rst_byte_2_i => cons_var_rst_byte_2_i,
--------------------------------------------
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
var3_rdy_o => var3_rdy_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
var3_rdy_o => var3_rdy_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o
---------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Rx_Bytes_Counter: WF_incr_counter
---------------------------------------------------------------------------------------------------
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
port map(
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
var_i => s_var,
------------------------------------
prod_data_length_o => s_prod_data_length
------------------------------------
);
-- -- -- -- -- -- -- -- -- -- --
prod_data_length_o <= s_prod_data_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Counter that counts the number of produced bytes
Produced_Bytes_Counter: WF_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
reinit_counter_i => s_rst_tx_bytes_counter,
incr_counter_i => s_inc_tx_bytes_counter,
---------------------------------------------
counter_o => s_rx_bytes_c,
counter_is_full_o => open
counter_o => s_prod_bytes_c,
counter_is_full_o => open
---------------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Tx_Bytes_Counter: WF_incr_counter
-- -- -- -- -- -- -- -- -- -- --
-- when s_prod_data_length bytes have been counted,the signal s_prod_data_length_match is activated
s_prod_data_length_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_length) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Counter that counts the number of bytes being received by the wf_rx_deserializer unit.
--! The same counter is used for the bytes of an ID_DAT frame or a consumed RP_DAT frame
--! (that is why the name of the counter is s_rx_bytes_c and not s_cons_bytes_c).
Rx_Bytes_Counter: WF_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => s_rst_tx_bytes_counter,
incr_counter_i => s_inc_tx_bytes_counter,
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
---------------------------------------------
counter_o => s_tx_bytes_c,
counter_is_full_o => open
counter_o => s_rx_bytes_c,
counter_is_full_o => open
---------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_tx_data_length bytes have been counted, the signal s_tx_data_length_match is activated
s_tx_data_length_match <= '1' when s_tx_bytes_c = unsigned(s_tx_data_length) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Rx_Tx_Bytes_Counters_Arg: process (s_id_dat_frame_ok, s_consuming, tx_request_byte_p_i,
s_producing, rx_byte_ready_p_i, s_rx_bytes_c, s_tx_bytes_c)
Arguments_For_Both_Bytes_Counters: process (s_id_dat_frame_ok, s_consuming, tx_request_byte_p_i,
s_producing, rx_byte_ready_p_i, s_rx_bytes_c, s_prod_bytes_c)
begin
if s_id_dat_frame_ok = '1' then
......@@ -586,7 +618,7 @@ begin
elsif s_producing = '1' then
s_rst_tx_bytes_counter <= '0';
s_inc_tx_bytes_counter <= tx_request_byte_p_i;
s_tx_byte_index <= std_logic_vector (resize(s_tx_bytes_c, s_tx_byte_index'length));
s_tx_byte_index <= std_logic_vector (resize(s_prod_bytes_c, s_tx_byte_index'length));
s_rst_rx_bytes_counter <= '1';
s_inc_rx_bytes_counter <= '0';
......@@ -602,20 +634,26 @@ begin
end if;
end process;
tx_rx_byte_index_o <= s_tx_byte_index when s_producing = '1'
else s_rx_byte_index;
prod_cons_byte_index_o <= s_tx_byte_index when s_producing = '1'
else s_rx_byte_index;
---------------------------------------------------------------------------------------------------
-- Turnaround & Silence times --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Managing the counter that counts either turnaround or silence times in uclk ticks.
-- The same counter is used in both cases. The signal s_time_counter_top initializes the counter
-- to either the turnaround or the silence time.
Response_and_Silence_Time_Counter: WF_decr_counter
Turnaround_and_Silence_Time_Counter: WF_decr_counter
generic map(g_counter_lgth => 15)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
nfip_urst_i => nfip_urst_i,
counter_top => s_time_counter_top,
counter_load_i => s_load_time_c,
counter_load_i => s_load_time_counter,
counter_decr_p_i => '1',
counter_o => s_time_c,
---------------------------------------
......@@ -624,8 +662,8 @@ Response_and_Silence_Time_Counter: WF_decr_counter
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of turnaround and silence times information (in equivalent number of uclk ticks) from
-- the c_TIMEOUTS_TABLE declared in the WF_package unit.
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_package unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
......@@ -633,43 +671,48 @@ Response_and_Silence_Time_Counter: WF_decr_counter
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Response_and_Silence_Time_Counter_Arg: process (s_prod_wait_resp_time, s_turnaround_time, s_cons_wait_FSS,
s_silence_time, s_id_dat_frame_ok, s_produce_or_consume)
Turnaround_and_Silence_Time_Counter_Arg: process (s_prod_wait_turnar_time, s_turnaround_time,
s_id_dat_frame_ok, s_produce_or_consume,
s_cons_wait_FSS, s_silence_time)
begin
if s_id_dat_frame_ok = '1' and s_produce_or_consume = "10" then
s_load_time_c <= '1'; -- counter loads
s_time_counter_top <= s_turnaround_time;
s_load_time_counter <= '1'; -- counter loads
s_time_counter_top <= s_turnaround_time;
elsif s_id_dat_frame_ok = '1' and s_produce_or_consume = "01" then
s_load_time_c <= '1'; -- counter loads
s_time_counter_top <= s_silence_time;
s_load_time_counter <= '1'; -- counter loads
s_time_counter_top <= s_silence_time;
elsif s_prod_wait_resp_time = '1' then
s_load_time_c <= '0'; -- counter counts
s_time_counter_top <= s_silence_time;
elsif s_prod_wait_turnar_time = '1' then
s_load_time_counter <= '0'; -- counter counts
s_time_counter_top <= s_silence_time;
elsif s_cons_wait_FSS = '1' then
s_load_time_c <= '0'; -- counter counts
s_time_counter_top <= s_silence_time;
s_load_time_counter <= '0'; -- counter counts
s_time_counter_top <= s_silence_time;
else
s_load_time_c <= '1';
s_time_counter_top <= s_silence_time;
s_load_time_counter <= '1';
s_time_counter_top <= s_silence_time;
end if;
end process;
--------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Recognition of the Identifier field of a received ID_DAT frame --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! The following two processes: id_dat_var_identifier and id_dat_var manage the
--! signals s_var_id, s_var_aux and s_var. All of them are used to keep the value of the
--! ID_DAT.Identifier.Variable byte of the incoming ID_DAT frame, but change their value on
--! different moments:
--! s_var_id: is constantly following the incoming byte rx_byte_i
--! s_var_aux: locks to the value of s_var_id when the ID_DAT.Identifier.Variable byte
--! s_var_id : is constantly following the incoming byte rx_byte_i
--! s_var_aux : locks to the value of s_var_id when the ID_DAT.Identifier.Variable byte
--! is received (s_load_var_aux = 1)
--! s_var: locks to the value of s_var_aux at the end of the ID_DAT frame (s_load_var = 1) if the
--! specified station address matches the SUBS configuration.
--! s_var : locks to the value of s_var_aux at the end of the ID_DAT frame (s_load_var = 1) if
--! the specified station address matches the SUBS configuration.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var_identifier: process (rx_byte_i)
......@@ -685,7 +728,7 @@ Response_and_Silence_Time_Counter: WF_decr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_load_var_aux <= s_id_dat_var_byte and rx_byte_ready_p_i;
s_load_var <= s_prod_wait_resp_time or s_consuming;
s_load_var <= s_prod_wait_turnar_time or s_consuming;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var: process (uclk_i)
......@@ -717,14 +760,15 @@ Response_and_Silence_Time_Counter: WF_decr_counter
var_o <= s_var; -- var_o takes a value at the end of the ID_DAT
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Combinatorial process Var_Characteristics: managment of the signals
--! s_produce_or_consume and s_broadcast_var, accroding to the value of s_var_aux.
Var_Characteristics: process (s_var_aux)
begin
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
for I in c_VARS_ARRAY'range loop
......@@ -740,15 +784,18 @@ Response_and_Silence_Time_Counter: WF_decr_counter
end loop;
if ((s_var_aux = var_2) or (s_var_aux = var_rst)) then
s_broadcast_var <= '1';
s_broadcast_var <= '1';
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief: essential buffering of output signals tx_last_byte_p_o, tx_byte_ready_p_o, tx_start_produce_p_o
-- Introducing delays --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Essential buffering of the signals tx_last_byte_p_o, tx_byte_ready_p_o,tx_start_prod_p_o
process (uclk_i)
begin
......@@ -765,22 +812,22 @@ Response_and_Silence_Time_Counter: WF_decr_counter
tx_last_byte_p_o <= s_tx_last_byte_p_d;
s_tx_byte_ready_p_d1 <= s_tx_byte_ready_p;
s_tx_byte_ready_p_d2 <= s_tx_byte_ready_p_d1;
s_tx_start_prod_p <= (s_prod_wait_resp_time and s_time_c_is_zero);
s_tx_start_prod_p <= (s_prod_wait_turnar_time and s_time_c_is_zero);
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tx_start_produce_p_o <= s_tx_start_prod_p;
tx_start_prod_p_o <= s_tx_start_prod_p;
s_tx_byte_ready_p <= s_producing and (tx_request_byte_p_i or s_tx_start_prod_p);
tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
s_tx_last_byte_p <= s_producing and s_tx_data_length_match and tx_request_byte_p_i;
rst_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
s_tx_last_byte_p <= s_producing and s_prod_data_length_match and tx_request_byte_p_i;
rst_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and prod_sending_mps_i;
rx_byte_ready_p_o <= s_consuming and rx_byte_ready_p_i;
cons_byte_ready_p_o <= s_consuming and rx_byte_ready_p_i;
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
---------------------------------------------------------------------------------------------------
......
wf_package.vhd
View file @ 40153778
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes, constants, and functions
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> egousiou: base_addr unsigned(8 downto 0) instead of std_logic_vector (9 downto 0),
--! to simplify calculations
--! turnaround times!!
--! broadcast: 91 instead of 04
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @file WF_package.vhd |
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package WF_package is
---------------------------------------------------------------------------------------------------
-- --
-- WF_package --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Definitions of constants, types, entities
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 11/01/2011
--
--
--! @version v0.03
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) \n
--! -> 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
--! std_logic_vector(9 downto 0) to simplify calculations; cleaning-up
--! -> 11/1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Package declaration for WF_package
--=================================================================================================
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
package WF_package is
constant c_QUARTZ_PERIOD : real := 25.0;
constant c_TX_CLK_BUFF_LGTH : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
constant c_QUARTZ_PERIOD : real := 25.0;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Constants regarding the CRC calculator
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculator --
---------------------------------------------------------------------------------------------------
constant c_GENERATOR_POLY_length : natural := 16;
-- Shift register xor mask
......@@ -39,36 +84,41 @@ package WF_package is
-- CRC check mask
constant c_VERIFICATION_MASK : std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Constants regarding the Manchester 2 coding
---------------------------------------------------------------------------------------------------
-- Constants regarding the Manchester 2 coding --
---------------------------------------------------------------------------------------------------
constant VP : std_logic_vector (1 downto 0) := "11";
constant VN : std_logic_vector (1 downto 0) := "00";
constant ONE : std_logic_vector (1 downto 0) := "10";
constant ZERO : std_logic_vector (1 downto 0) := "01";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
-- Constants regarding the ID_DAT and RP_DAT frame structure
constant PRE : std_logic_vector (15 downto 0) := ONE & ZERO & ONE & ZERO & ONE & ZERO & ONE & ZERO;
constant FSD : std_logic_vector (15 downto 0) := ONE & VP & VN & ONE & ZERO & VN & VP & ZERO;
constant FES : std_logic_vector (15 downto 0) := ONE & VP & VN & VP & VN & ONE & ZERO & ONE;
constant FSS : std_logic_vector (31 downto 0) := PRE & FSD;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants regarding the Control and PDU_TYPE bytes of ID_DAT and RP_DAT frames --
---------------------------------------------------------------------------------------------------
-- Constants concerning the control byte of an ID_DAT and RP_DAT frames and the PDU_TYPE byte of
-- a consumed or produced variable
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000010";
constant c_PROD_CONS_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
---------------------------------------------------------------------------------------------------
-- Constants regarding the nanoFIP status bits --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Constants concerning the nanoFIP status bits
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_TLER_INDEX : integer := 4;
......@@ -77,16 +127,18 @@ package WF_package is
constant c_T_WDER_INDEX : integer := 7;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants regarding the MPS status bits --
---------------------------------------------------------------------------------------------------
-- Constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
-- Constants concerning the position of certain bytes in the frame structure
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
......@@ -97,8 +149,9 @@ package WF_package is
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the P3_LGTH[2:0] settings --
---------------------------------------------------------------------------------------------------
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
......@@ -113,9 +166,11 @@ package WF_package is
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the bit rate --
---------------------------------------------------------------------------------------------------
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
......@@ -139,10 +194,12 @@ package WF_package is
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the turnaround and silence times --
---------------------------------------------------------------------------------------------------
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
type t_timeouts is
record
turnaround : integer;
......@@ -173,10 +230,12 @@ package WF_package is
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the consumed & produced variables --
---------------------------------------------------------------------------------------------------
-- Construction of a table that gathers main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
......@@ -265,9 +324,23 @@ package WF_package is
others => x"ff")));
---------------------------------------------------------------------------------------------------
-- Constant regarding the transmitters (wf_tx_serializer) clock --
---------------------------------------------------------------------------------------------------
constant c_TX_CLK_BUFF_LGTH : natural := 4;
---------------------------------------------------------------------------------------------------
-- Components Declaration: --
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
component WF_inputs_synchronizer is
......@@ -587,23 +660,23 @@ end component wf_production;
rx_crc_wrong_p_i : in std_logic;
rx_byte_ready_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_CRC_FES_ok_p_i : in std_logic;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
tx_sending_mps_i : in std_logic;
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
produce_wait_turnar_time : in std_logic;
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
prod_sending_mps_i : in std_logic;
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
tx_byte_ready_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
tx_start_prod_p_o : out std_logic;
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_length_o : out std_logic_vector (7 downto 0);
cons_byte_ready_p_o : out std_logic;
rst_status_bytes_o : out std_logic;
rst_rx_unit_p_o : out std_logic;
var_o : out t_var;
......@@ -868,12 +941,12 @@ end component wf_production;
---------------------------------------------------------------------------------------------------
component WF_prod_data_lgth_calc is
port (
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
---------------------------------------------------------------
tx_data_length_o : out std_logic_vector(7 downto 0)
prod_data_length_o : out std_logic_vector(7 downto 0)
---------------------------------------------------------------
);
end component WF_prod_data_lgth_calc;
......@@ -882,9 +955,9 @@ end component wf_production;
---------------------------------------------------------------------------------------------------
component WF_cons_frame_validator is
port (
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
rx_crc_wrong_p_i : in std_logic;
rx_fss_crc_fes_viol_ok_p_i : in std_logic;
var_i : in t_var;
......@@ -901,20 +974,20 @@ end component wf_production;
---------------------------------------------------------------------------------------------------
component WF_var_rdy_generator is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_urst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_urst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
---------------------------------------------------------------
);
end component WF_var_rdy_generator;
......
wf_prod_data_lgth_calc.vhd
View file @ 40153778
......@@ -81,16 +81,16 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- Signal from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_engine_control
tx_data_length_o : out std_logic_vector(7 downto 0)
prod_data_length_o : out std_logic_vector(7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -100,7 +100,7 @@ end entity WF_prod_data_lgth_calc;
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -124,13 +124,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
s_prod_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
s_prod_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -154,35 +154,35 @@ begin
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_tx_data_length <= to_unsigned(5, s_tx_data_length'length);
s_prod_data_length <= to_unsigned(5, s_prod_data_length'length);
else -- 7 bytes (counting starts from 0)
s_tx_data_length <= to_unsigned(6, s_tx_data_length'length);
s_prod_data_length <= to_unsigned(6, s_prod_data_length'length);
end if;
else
if nostat_i = '0' then
s_tx_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
else
s_tx_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst => -- to avoid Warnings from Synthesiser
s_tx_data_length <= (others => '0');
s_prod_data_length <= (others => '0');
when others =>
s_tx_data_length <= (others => '0');
s_prod_data_length <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
tx_data_length_o <= std_logic_vector (s_tx_data_length);
prod_data_length_o <= std_logic_vector (s_prod_data_length);
end architecture rtl;
......
wf_status_bytes_gen.vhd
View file @ 40153778
......@@ -182,6 +182,7 @@ begin
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_txer
if (fd_wdgn_i = '0') then -- FIELDRIVE transmission error
......@@ -195,36 +196,19 @@ begin
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
s_nFIP_status_byte(c_R_TLER_INDEX) <= nfip_status_r_tler_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
s_nFIP_status_byte(c_R_FCSER_INDEX) <= nfip_status_r_fcser_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_tler_i = '1')) then
-- s_nFIP_status_byte(c_R_TLER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. arrived for this
-- station with wrong PDU_TYPE,
-- Control or Length bytes
-- end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_fcser_p_i = '1')) then
-- s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. with a wrong
-- CRC arrived for this station
-- end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
end if;
......
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