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nanoFIP - Gateware
Commit 297713da authored by egousiou's avatar egousiou
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wf_engine_control: mistake when id_dat with wrong crc arrives corrected 

aesthetics: trailing whitespaces deleted from all the units

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@173 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent c2a427ea
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DualClkRAM.vhd
View file @ 297713da
......@@ -32,10 +32,10 @@ use PROASIC3.all;
--
--
--! @brief Instantiation of a template ProAsic3 RAM4K9 memory component with
--! o word width : 8 bits and
--! o word width : 8 bits and
--! o depth : 512 bytes.
--
--
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
......@@ -50,23 +50,23 @@ use PROASIC3.all;
--
--! \n<b>Dependencies:</b>\n
--! ProASIC3 lib \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
--! address is given (otherwise it was 2 clock cycles later) slack
--! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
--! address is given (otherwise it was 2 clock cycles later) slack
--! checked and is ok! code cleaned-up and commented \n
--! ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -75,12 +75,12 @@ use PROASIC3.all;
entity DualClkRAM is
port(
-- INPUTS
-- Inputs concerning port A
-- INPUTS
-- Inputs concerning port A
CLKA : in std_logic; --! clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port B
CLKB : in std_logic; --! clock B for synchronous read/ write operations
......@@ -93,10 +93,10 @@ entity DualClkRAM is
-- OUTPUTS
-- Output concerning port A
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
......@@ -107,7 +107,7 @@ end DualClkRAM;
--=================================================================================================
architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- !@brief component RAM4K9 :
--! General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
--! pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9.
......@@ -122,7 +122,7 @@ architecture RAM4K9 of DualClkRAM is
--! Switching between Read and Write modes for the respective ports.
--! A Low indicates Write operation and a High indicates a Read.
--! BLKA, BLKB :
--! BLKA, BLKB :
--! Active low enable for the respective ports.
--! PIPEA, PIPEB :
......@@ -133,7 +133,7 @@ architecture RAM4K9 of DualClkRAM is
--! WMODEA, WMODEB :
--! Configuration of the behavior of the output when the RAM is in the Write mode.
--! A Low on this signal makes the output retain data from the previous Read. A High indicates a
--! A Low on this signal makes the output retain data from the previous Read. A High indicates a
--! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
......@@ -160,14 +160,14 @@ architecture RAM4K9 of DualClkRAM is
);
end component;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component VCC
component VCC
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component GND
component GND
......@@ -187,9 +187,9 @@ begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief: Instantiation of the component RAM4K9.
--! The following configuration has been applied:
--! The following configuration has been applied:
--! o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
--! o word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open)
--! o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
......@@ -199,10 +199,10 @@ begin
A9D8DualClkRAM_R0C0 : RAM4K9
port map (
-- INPUTS
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
......@@ -236,7 +236,7 @@ begin
PIPEA => GROUND,
WMODEA => GROUND,
-- inputs concerning port B
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
......@@ -275,7 +275,7 @@ begin
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
......@@ -287,7 +287,7 @@ begin
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
......
nanofip.vhd
View file @ 297713da
......@@ -21,14 +21,14 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- --
-- nanoFIP --
-- --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--
--! @brief
--! @brief
--! The nanoFIP is an FPGA component implementing the WorldFIP protocol that can be used in field
--! devices. The nanoFIP is designed to be radiation tolerant by using different single event upset
--! mitigation techniques such as Triple Module Redundancy and several reset possibilities. The
......@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! frame:
--! ___________ ______ _______ ______ ___________ _______
--! |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__|
--!
--!
--! Figure 1 : ID_DAT frame structure
--!
--! nanoFIP is handling the following set of variables addressed by:
......@@ -84,7 +84,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! (E0..h), validated by station address as data
--! o FIELDRIVE reset output (FD_RSTN) by the reset broadcast consumed variable (E0..h),
--! validated by station address as data
--!
--!
--! nanoFIP's main building blocks are (Figure 3):
--! o WF_inputs_synchronizer : for the synchronization of the input signals with the user
--! or the WISHBONE clock.
......@@ -93,17 +93,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_tx_rx_osc : for the generation of the clocks used by the transmitter and
--! receiver for the data serialization and deserialization.
--! o WF_consumption : for the processing of consumed variables, from the deserialization
--! to the bytes storage and validation.
--! to the bytes storage and validation.
--! o WF_production : for the processing of produced variables, from the bytes
--! retrieval to the serialization.
--! o WF_engine_control : for the processing of the ID_DAT frames and the coordination of the
--! WF_consumption and WF_production units.
--! WF_consumption and WF_production units.
--! o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the
--! generation of the S_ID.
--! o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control
--! signals.
--!
--! _____________ __________________________ _____________
--! _____________ __________________________ _____________
--! | | | | | |
--! | | | WF_tx_rx_osc | | |
--! | | | | | |
......@@ -134,7 +134,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | constr_dec | ___________________________ | |
--! | | | WF_wb_controller | | |
--! |_____________| |___________________________| |_____________|
--!
--!
--! Figure 3: nanoFIP block diagram
--!
--! The design is based on the NanoFIP functional specification v1.3 document, available at:
......@@ -145,7 +145,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--
--! @date 15/01/2011
--
......@@ -153,7 +153,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.04
--
--
--! @details\n
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -175,16 +175,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 30/06/2009 v0.010 EB First version \n
--! -> 06/07/2009 v0.011 EB Dummy blocks \n
--! -> 07/07/2009 v0.011 EB Comments \n
--! -> 15/09/2009 v0.v2 PA
--! -> 15/09/2009 v0.v2 PA
--! -> 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added)
--! -> 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
--! -> 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
--! -> 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -207,19 +207,19 @@ entity nanofip is
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding (station address)
-- FIELDRIVE
-- FIELDRIVE
fd_rxcdn_i : in std_logic; --! Reception activity detection, active low
fd_rxd_i : in std_logic; --! Receiver data
fd_txer_i : in std_logic; --! Transmitter error
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
-- User Interface, General signals
nostat_i : in std_logic; --! No NanoFIP status with produced data
rstin_i : in std_logic; --! Initialisation control, active low
rstin_i : in std_logic; --! Initialization control, active low
--! Resets nanoFIP & the FIELDRIVE
rstpon_i : in std_logic; --! Power On Reset, active low
......@@ -238,7 +238,7 @@ entity nanofip is
-- User Interface, WISHBONE Slave
wclk_i : in std_logic; --! WISHBONE clock; may be independent of uclk
adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address
cyc_i : in std_logic; --! WISHBONE cycle
cyc_i : in std_logic; --! WISHBONE cycle
dat_i : in std_logic_vector (15 downto 0);--! dat_i(7 downto 0) : WISHBONE data in, memory mode
--! dat_i(15 downto 0): data in, stand-alone mode
......@@ -255,18 +255,18 @@ entity nanofip is
-- WorldFIP settings
s_id_o : out std_logic_vector (1 downto 0);--! Identification selection
-- FIELDRIVE
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_rstn_o : out std_logic; --! Initialization control, active low
fd_txck_o : out std_logic; --! Line driver half bit clock
fd_txd_o : out std_logic; --! Transmitter data
fd_txena_o : out std_logic; --! Transmitter enable
-- User Interface, General signals
rston_o : out std_logic; --! Reset output, active low
......@@ -331,30 +331,29 @@ architecture struc of nanofip is
--=================================================================================================
-- architecture begin
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- WF_reset_unit --
---------------------------------------------------------------------------------------------------
reset_unit : WF_reset_unit
reset_unit : WF_reset_unit
port map (
uclk_i => uclk_i,
wb_clk_i => wclk_i,
rstin_a_i => rstin_i,
rstpon_i => rstpon_i,
rstpon_a_i => rstpon_i,
rate_i => rate_i,
rst_i => rst_i,
var_i => s_var_from_control,
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
assert_RSTON_p_i => s_assert_RSTON_p,
---------------------------------------------------------
nFIP_rst_o => s_rst,
nFIP_rst_o => s_rst,
wb_rst_o => s_wb_rst,
rston_o => rston_o,
fd_rstn_o => fd_rstn_o);
fd_rstn_o => fd_rstn_o);
---------------------------------------------------------
......@@ -419,7 +418,7 @@ begin
wb_clk_i => wclk_i,
wb_data_i => dat_i(7 downto 0),
wb_adr_i => adr_i(8 downto 0),
wb_ack_prod_p_i => s_wb_ack_prod,
wb_ack_prod_p_i => s_wb_ack_prod,
slone_data_i => dat_i,
var1_acc_a_i => var1_acc_i,
var2_acc_a_i => var2_acc_i,
......@@ -472,33 +471,33 @@ begin
-- WF_engine_control --
---------------------------------------------------------------------------------------------------
engine_control : WF_engine_control
engine_control : WF_engine_control
port map (
uclk_i => uclk_i,
nfip_rst_i => s_rst,
tx_byte_request_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_rx_fss_decoded_p,
rx_byte_i => s_rx_byte,
nfip_rst_i => s_rst,
tx_byte_request_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_rx_fss_decoded_p,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p,
rate_i => rate_i,
subs_i => subs_i,
p3_lgth_i => p3_lgth_i,
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
slone_i => slone_i,
nostat_i => nostat_i,
---------------------------------------------------------
var_o => s_var_from_control,
tx_start_p_o => s_start_tx_p ,
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
tx_start_p_o => s_start_tx_p ,
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_lgth_o => s_data_lgth_from_control,
rx_rst_p_o => s_rx_rst_p);
---------------------------------------------------------
var1_rdy_o <= s_var1_rdy;
var2_rdy_o <= s_var2_rdy;
var1_rdy_o <= s_var1_rdy;
var2_rdy_o <= s_var2_rdy;
var3_rdy_o <= s_var3_rdy;
......@@ -506,7 +505,7 @@ begin
---------------------------------------------------------------------------------------------------
-- WF_model_constr_decoder --
---------------------------------------------------------------------------------------------------
model_constr_decoder : WF_model_constr_decoder
model_constr_decoder : WF_model_constr_decoder
port map (
uclk_i => uclk_i,
nfip_rst_i => s_rst,
......@@ -529,13 +528,13 @@ begin
wb_clk_i => wclk_i,
wb_rst_i => rst_i,
wb_stb_i => stb_i,
wb_cyc_i => cyc_i,
wb_cyc_i => cyc_i,
wb_we_i => we_i,
wb_adr_id_i => adr_i (9 downto 7),
wb_adr_id_i => adr_i (9 downto 7),
---------------------------------------------------------------
wb_ack_prod_p_o => s_wb_ack_prod,
wb_ack_p_o => ack_o);
---------------------------------------------------------------
---------------------------------------------------------------
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 297713da
......@@ -6,9 +6,9 @@
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -28,14 +28,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief The unit provides the memory triplication, transparently to the outside world.
--! The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter.
--! The memory is dual port; port A is used for reading only, port B for writing only.
--!
--! Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
--
--
--! Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
......@@ -48,23 +48,23 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b>\n
--! DualClkRAM.vhd \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -76,29 +76,29 @@ entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (g_ram_data_lgth : integer; -- length of data word
g_ram_addr_lgth : integer); -- memory depth
port (
-- INPUTS
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
-- Inputs concerning port B
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
end WF_DualClkRAM_clka_rd_clkb_wr;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
......@@ -109,32 +109,32 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
--! The component DualClkRam is generated three times.
--! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array s_data_o_A_array.
G_memory_triplication: for I in 0 to 2 generate
G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
UDualClkRam : DualClkRam
port map (
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
......@@ -144,7 +144,7 @@ begin
end generate;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial Majority_Voter
Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
wf_bits_to_txd.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
......@@ -54,21 +54,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
--! -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
--! need for tx_clk_p_buff signal
--! -> 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
--! becomes 1 for the 1st bit of preamble
--! signals s_tx_enable & s_start_tx_enable removed for simplification
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -78,7 +78,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_bits_to_txd is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
......@@ -94,12 +94,12 @@ entity WF_bits_to_txd is
sending_fes_i : in std_logic; --! -------"----"-----"--------
stop_transmission_i : in std_logic; --! -------"----"-----"--------
txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte
-- Signals from the WF_tx_osc unit
tx_clk_p_i : in std_logic; --!clk for transmission synchronization
tx_clk_p_i : in std_logic; --!clk for transmission synchronization
-- OUTPUTS
-- nanoFIP FIELDRIVE outputs
txd_o : out std_logic; --! FD_TXD
......@@ -116,7 +116,7 @@ architecture rtl of WF_bits_to_txd is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -133,7 +133,7 @@ begin
else
if tx_clk_p_i = '1' then
if tx_clk_p_i = '1' then
if sending_fss_i = '1' then
txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
......@@ -148,7 +148,7 @@ begin
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
txd_o <= '0';
end if;
end if;
......@@ -162,7 +162,7 @@ begin
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
--! same moment as the first bit of the PRE starts being delivered and stays asserted until the
--! end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -174,7 +174,7 @@ begin
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enable with the
end if; -- the delivery of the 1st FSS bit
-- FD_TXD (FSS) :________|-----|___________|--------
......@@ -183,7 +183,7 @@ begin
-- FD_TXENA :________|--------------------------
else
tx_enable_o <= '0';
end if;
end if;
end if;
end if;
......
wf_cons_bytes_processor.vhd
View file @ 297713da
......@@ -27,12 +27,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit is consuming the RP_DAT data bytes that are arriving from the
--! @brief The unit is consuming the RP_DAT data bytes that are arriving from the
--! WF_fd_receiver, according to the following:
--!
--! o If the consumed variable had been a var_1 or a var_2:
--!
--! o If the operation is in memory mode : the unit is registering the
--! o If the operation is in memory mode : the unit is registering the
--! application-data bytes along with the PDU_TYPE, Length and MPS bytes in the
--! Consumed memories
--!
......@@ -44,9 +44,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! Note: The validity of the consumed bytes (stored in the memory or transfered to DATO
--! or transfered to the WF_reset_unit) is indicated by the "nanoFIP User Interface,
--! NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal signals
--! NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal signals
--! rst_nFIP_and_FD_p/ assert_RSTON_p, which are treated in the WF_cons_outcome unit and
--! are assessed after the end of the reception of a complete frame.
--! are assessed after the end of the reception of a complete frame.
--!
--!
--! Reminder:
......@@ -64,7 +64,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--
--! @date 15/12/2010
--
......@@ -72,7 +72,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details\n
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -98,9 +98,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! --> separate unit for the wb_ack treatment
--! --> two constant!
--! @todo
--
---------------------------------------------------------------------------------------------------
......@@ -112,7 +110,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_cons_bytes_processor is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
......@@ -120,7 +118,7 @@ port (
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
......@@ -133,17 +131,17 @@ port (
-- starting from 0, it counts all the
-- bytes after the FSS&before the FES
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- OUTPUTS
-- nanoFIP User Interface, WISHBONE Slave output
data_o : out std_logic_vector (15 downto 0);--! data out bus
data_o : out std_logic_vector (15 downto 0);--! data out bus
-- Signals to the WF_cons_outcome unit
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Control byte
cons_lgth_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Length byte
cons_pdu_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT PDY_TYPE byte
cons_pdu_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT PDY_TYPE byte
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! received var_rst, 1st data byte
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! received var_rst, 2nd data byte
);
......@@ -157,10 +155,9 @@ end entity WF_cons_bytes_processor;
architecture rtl of WF_cons_bytes_processor is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned (7 downto 0);
signal s_base_addr : unsigned (8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
......@@ -170,12 +167,11 @@ architecture rtl of WF_cons_bytes_processor is
--=================================================================================================
begin
two <= to_unsigned (2, two'length);
---------------------------------------------------------------------------------------------------
-- Consumed & Consumed Broadcast RAM --
-- Storage (by the unit) & retreival (by the user) of consumed bytes --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a Dual Port Consumed RAM (for both the consumed and consumed broadcast
--! variables).
--! Port A is connected to WISHBONE interface for the readings from the user and
......@@ -186,18 +182,18 @@ begin
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- remaining 7 : address of a byte inside the blck
port map (
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i, -- address of byte to be read
clk_portb_i => uclk_i, -- 40 MHz clock
clk_portb_i => uclk_i, -- 40 MHz clock
addr_portb_i => s_addr, -- address of byte to be written
data_portb_i => byte_i, -- byte to be written
write_en_portb_i => s_write_byte_to_mem_p,-- write enable
--------------------------------------------
data_porta_o => s_mem_data_out); -- output byte read
--------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -207,19 +203,19 @@ begin
--! s_slone_write_byte_p, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O
--! takes the byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_slone_data <= (others => '0'); -- bus initialization
else
if s_slone_write_byte_p(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
if s_slone_write_byte_p(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
s_slone_data(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
end if;
if s_slone_write_byte_p(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
......@@ -234,9 +230,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- In stand-alone mode the 16 bits DAT_O fills up with the s_slone_data.
-- In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
data_o <= s_slone_data when slone_i = '1'
else "00000000" & s_mem_data_out;
else "00000000" & s_mem_data_out;
......@@ -248,7 +244,7 @@ begin
--! In memory mode the treatment of a var_1 is identical to the one of a var2; only the base address
--! of the memory differs.
--! Bytes are consumed even if any of the Control, PDU_TYPE, Length, CRC & FES byte or the manch.
--! encoding of the consumed frame are incorrect.
--! It is the VAR_RDY signal that signals the user for the validity of the consumed data.
......@@ -275,46 +271,46 @@ begin
s_addr <= std_logic_vector (unsigned(byte_index_i)+s_base_addr - 1); -- memory address of
-- the byte to be written
-- (-1 bc the Ctrl
-- byte is not written)
-- byte is not written)
Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i, byte_ready_p_i,s_cons_lgth_byte)
Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i,two,byte_ready_p_i,s_cons_lgth_byte)
begin
case var_i is
case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_1 =>
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr;-- base address
-- from WF_package
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
if slone_i = '0' then
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
s_slone_write_byte_p <= (others => '0');
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then -- less or eq
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq
s_write_byte_to_mem_p <= byte_ready_p_i; -- "Length" amount of
-- bytes are written
--(to avoid writing CRC!)
else
s_write_byte_to_mem_p <= '0';
else
s_write_byte_to_mem_p <= '0';
end if;
else -- before the reception
s_write_byte_to_mem_p <= byte_ready_p_i; -- of the Length byte
end if; -- all the bytes (after
-- Control) are written
-- Control) are written
else
s_write_byte_to_mem_p <= '0';
end if;
......@@ -326,99 +322,99 @@ begin
s_write_byte_to_mem_p <= '0';
if byte_index_i = c_1st_DATA_BYTE_INDEX then -- 1st byte to be transferred
s_slone_write_byte_p <= '0'& byte_ready_p_i;
s_slone_write_byte_p <= '0'& byte_ready_p_i;
elsif byte_index_i = c_2nd_DATA_BYTE_INDEX then -- 2nd byte to be transferred
s_slone_write_byte_p <= byte_ready_p_i & '0';
s_slone_write_byte_p <= byte_ready_p_i & '0';
else
s_slone_write_byte_p <= (others=>'0');
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_2 =>
-- same treatment as var 1 on a different memory location (base_addr)
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr;
cons_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr;
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then
if byte_index_i > c_LGTH_BYTE_INDEX then
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then
if byte_index_i > c_LGTH_BYTE_INDEX then
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then
s_write_byte_to_mem_p <= byte_ready_p_i;
else
s_write_byte_to_mem_p <= '0';
else
s_write_byte_to_mem_p <= '0';
end if;
else
s_write_byte_to_mem_p <= byte_ready_p_i;
end if;
s_write_byte_to_mem_p <= byte_ready_p_i;
end if;
else
s_write_byte_to_mem_p <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- --
-- stand-alone mode does not treat consumed broadcast vars
else
else
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_rst =>
s_write_byte_to_mem_p <= '0'; -- no writing in memory for the reset var
s_slone_write_byte_p <= (others => '0');
s_base_addr <= (others => '0');
s_base_addr <= (others => '0');
if ((byte_ready_p_i = '1')and(byte_index_i = c_1st_DATA_BYTE_INDEX)) then -- 1st byte
cons_var_rst_byte_1_o <= byte_i;
cons_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
elsif ((byte_ready_p_i='1')and(byte_index_i=c_2nd_DATA_BYTE_INDEX)) then -- 2nd byte
cons_var_rst_byte_2_o <= byte_i;
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
else
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_3 | var_presence | var_identif | var_whatever =>
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
end case;
......@@ -435,7 +431,7 @@ end process;
--! VAR2_RDY(for a var_2), assert_rston_p & rst_nfip_and_fd_p(for a var_rst).
Register_Ctrl_PDU_LGTH_bytes: process (uclk_i)
begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -446,13 +442,13 @@ end process;
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only for consumed vars
if ((byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1')) then
cons_ctrl_byte_o <= byte_i;
if ((byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1')) then
cons_ctrl_byte_o <= byte_i;
elsif ((byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1')) then
elsif ((byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1')) then
cons_pdu_byte_o <= byte_i;
elsif ((byte_index_i = c_LGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
elsif ((byte_index_i = c_LGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
s_cons_lgth_byte <= byte_i;
end if;
......@@ -465,7 +461,7 @@ end process;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_cons_lgth_byte;
end architecture rtl;
......
wf_cons_outcome.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -40,7 +40,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY.
--! o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by
--! the WF_status_bytes_generator unit (nanoFIP status byte, bit 4).
--! o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
--! o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
--!
--!
--! Reminder:
......@@ -62,7 +62,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.05
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -74,7 +74,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 10/2010 v0.01 EG First version \n
......@@ -85,11 +85,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
--! -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -100,19 +100,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_cons_outcome is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_fd_receiver unit
rx_fss_crc_fes_manch_ok_p_i : in std_logic; --! indication of a frame with correct FSS, FES, CRC
rx_fss_crc_fes_manch_ok_p_i : in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding; pulse upon FES detection
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC or manch.
......@@ -121,7 +121,7 @@ entity WF_cons_outcome is
-- Signals from the WF_consumption unit
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Length byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT PDU_TYPE byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT PDU_TYPE byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 1st data-byte
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 2nd data-byte
......@@ -163,28 +163,28 @@ architecture rtl of WF_cons_outcome is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with
---------------------------------------------------------------------------------------------------
--!@brief Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with
--! respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and to the
--! Manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! the checks of the FSS, CRC, FES and of the manch. encoding.
--! the checks of the FSS, CRC, FES and of the manch. encoding.
--! To check the correctness of the the RP_DAT.Data.Length byte, we compare it to the value of the
--! rx_byte_index, when the FES is detected (pulse rx_fss_crc_fes_manch_ok_p_i).
--! Note: In addition to the &Length bytes, the rx_byte_index also counts the Control, PDU_TYPE,
--! Length, the 2 CRC and the FES bytes (and counting starts from 0!).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! The same process is also used for the generation of the of the nanoFIP status byte, bit 4, that
--! indicates a received PDU_TYPE or Length byte error in a consumed RP_DAT frame.
--! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_manch_ok_p_i or by the
--! indicates a received PDU_TYPE or Length byte error in a consumed RP_DAT frame.
--! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_manch_ok_p_i or by the
--! rx_crc_or_manch_wrong_p_i.
Frame_Validation: process (uclk_i)
Frame_Validation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -199,7 +199,7 @@ begin
(unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then --LGTH byte check
s_cons_frame_ok_p <= '1';
else
else
s_cons_frame_ok_p <= '0';
end if;
......@@ -221,7 +221,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR_RDY_Generation:
--!@brief Synchronous process VAR_RDY_Generation:
--! Memory Mode:
--! Since the three memories (consumed, consumed broadcast, produced) are independent, when a
......@@ -230,16 +230,16 @@ begin
--! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed memory.
--! The signal is asserted only after the reception of a correct RP_DAT frame.
--! It is de-asserted after the reception of a correct var_1 ID_DAT frame.
--! It is de-asserted after the reception of a correct var_1 ID_DAT frame.
--! VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the
--! consumed broadcast memory. The signal is asserted only after the reception of a correct
--! consumed broadcast RP_DAT frame. It is de-asserted after the reception of a correct var_2
--! ID_DAT frame.
--! ID_DAT frame.
--! Stand-alone Mode:
--! Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed
--! Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed
--! bytes are independent. Stand-alone mode though does not treat the consumed broadcast variable.
--! VAR1_RDY (for consumed vars): signals that the user can safely retrieve data from the DAT_O
......@@ -254,7 +254,7 @@ begin
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
--! until the end of the reception.
VAR_RDY_Generation: process (uclk_i)
VAR_RDY_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -268,14 +268,14 @@ begin
case var_i is
when var_1 => -- nanoFIP consuming
--------------------
--------------------
var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is 0
var2_rdy_o <= s_var2_received; -- VAR2_RDY retains its value
-- -- -- -- -- -- -- -- -- -- --
if s_cons_frame_ok_p = '1' then -- only if the received RP_DAT frame is correct,
-- the nanoFIP signals the user to retreive data
-- the nanoFIP signals the user to retreive data
s_var1_received <= '1'; -- note:the signal s_var1_received remains asser-
-- ted after the end of the cons_frame_ok_p pulse
end if;
......@@ -283,29 +283,29 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_2 => -- nanoFIP consuming broadcast
------------------------------
when var_2 => -- nanoFIP consuming broadcast
------------------------------
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
var1_rdy_o <= s_var1_received; -- VAR1_RDY retains its value
if slone_i = '0' and s_cons_frame_ok_p = '1' then
if slone_i = '0' and s_cons_frame_ok_p = '1' then
-- only in memory mode and if the received RP_DAT
s_var2_received <= '1'; -- frame is correct, the nanoFIP signals the user
-- to retreive data.
-- note:the signal s_var2_received remains asser-
end if; -- ted after the end of the cons_frame_ok_p pulse
end if; -- ted after the end of the cons_frame_ok_p pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
end case;
var2_rdy_o <= s_var2_received;
end case;
end if;
end if;
end process;
......@@ -313,31 +313,31 @@ begin
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed
--! reset var contains the station address
--!@ brief: Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed
--! reset var contains the station address
--! and assert_rston : signals that the 2nd byte of a consumed
--! reset var contains the station address
--! reset var contains the station address
Cons_Reset_Signals: process (uclk_i)
Cons_Reset_Signals: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_rst_nfip_and_fd <= '0';
s_assert_rston <= '0';
else
if var_i = var_rst then
if cons_var_rst_byte_1_i = subs_i then
s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until
s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current RP_DAT frame
if cons_var_rst_byte_2_i = subs_i then
if cons_var_rst_byte_2_i = subs_i then
s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until
s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current RP_DAT frame
else
s_rst_nfip_and_fd <= '0';
......
wf_consumption.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -39,7 +39,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
--! CRC bytes & manch. encoding) and the generation of the
--! "nanoFIP User Interface,NON-WISHBONE" outputs VAR1_RDY
--! and VAR2_RDY (for var_1, var_2) or of the internal
--! and VAR2_RDY (for var_1, var_2) or of the internal
--! signals for the nanoFIP and FIELDRIVE resets (var_rst).
--!
--! ___________________________________________________________
......@@ -59,12 +59,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________|
--! /\
--! ___________________________________________________________
--! | |
--! | |
--! | WF_fd_receiver |
--! |___________________________________________________________|
--! /\
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--! 0_____________________________FIELDBUS______________________________O
--!
--!
--! Important Notice : The WF_rx_deserializer is "blindly" responsible for the formation
......@@ -73,7 +73,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! external unit WF_engine_control is in charge of the ID_DATs.
--!
--! Note : In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
--! which of the instantiated units needs it.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -86,7 +86,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -96,17 +96,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--! ->
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -116,7 +116,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_consumption is
port (
-- INPUTS
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
......@@ -131,7 +131,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);
subs_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_outcome for checking if the 2 bytes of a var_rst match the station's addr
......@@ -154,7 +154,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
-- used by: WF_cons_bytes_processor for the managment of the Consumption RAM
......@@ -165,19 +165,19 @@ entity WF_consumption is
var_i : in t_var;
-- used by: WF_cons_bytes_processor and WF_cons_outcome
byte_index_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_bytes_processor for the reception coordination
-- used by: WF_cons_outcome for the validation of the Length byte
byte_index_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_bytes_processor for the reception coordination
-- used by: WF_cons_outcome for the validation of the Length byte
-----------------------------------------------------------------------------------------------
-- OUTPUTS
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
-- nanoFIP User Interface, WISHBONE Slave outputs
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);
-- Signals to the WF_produce
......@@ -197,41 +197,41 @@ end entity WF_consumption;
--=================================================================================================
architecture struc of WF_consumption is
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Bytes Processing --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_bytes_processor unit that is "consuming" data bytes
--! arriving from the WF_rx_deserializer, by registering them to the Consumed memories or by
--! transferring them to the "nanoFIP User Interface, NON_WISHBONE" output bus DAT_O.
Consumption_Bytes_Processor : WF_cons_bytes_processor
Consumption_Bytes_Processor : WF_cons_bytes_processor
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
byte_ready_p_i => rx_byte_ready_p_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_i => rx_byte_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
--------------------------------------------------------
data_o => data_o,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
cons_lgth_byte_o => s_cons_lgth_byte,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2);
--------------------------------------------------------
......@@ -239,7 +239,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Outcome --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_outcome unit that is generating :
--! the "nanoFIP User Interface, NON_WISHBONE" output signal R_TLER,
--! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2) or
......@@ -250,13 +250,13 @@ begin
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
rx_fss_crc_fes_manch_ok_p_i => rx_fss_crc_fes_manch_ok_p_i,
rx_crc_or_manch_wrong_p_i => rx_crc_or_manch_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
......@@ -268,11 +268,11 @@ begin
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o);
--------------------------------------------------------
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_crc.vhd
View file @ 297713da
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.04
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
......@@ -77,11 +77,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_crc is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_rx_deserializer/ WF_tx_serializer units
......@@ -89,14 +89,14 @@ entity WF_crc is
data_bit_ready_p_i : in std_logic; --! indicates the sampling moment of data_bit_i
start_crc_p_i : in std_logic; --! beginning of the CRC calculation
-- OUTPUTS
-- OUTPUTS
-- Signal to the WF_rx_deserializer unit
crc_ok_p_o : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
);
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)--!calculated CRC
);
end entity WF_crc;
......@@ -106,7 +106,7 @@ end entity WF_crc;
--=================================================================================================
architecture rtl of WF_crc is
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--=================================================================================================
......@@ -115,7 +115,7 @@ architecture rtl of WF_crc is
begin
---------------------------------------------------------------------------------------------------
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
......@@ -124,7 +124,7 @@ begin
s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
......@@ -139,7 +139,7 @@ begin
if nfip_rst_i = '1' then
s_q <= (others => '0');
else
if start_crc_p_i = '1' then
......@@ -154,21 +154,21 @@ begin
end if;
end process;
-- -- -- -- --
-- -- -- -- --
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
--! predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
--! c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin
if s_q = not c_CRC_VERIFIC_MASK then
if s_q = not c_CRC_VERIF_POLY then
crc_ok_p_o <= data_bit_ready_p_i;
......
wf_decr_counter.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -37,23 +37,23 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -64,7 +64,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
entity WF_decr_counter is
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
......@@ -75,11 +75,11 @@ entity WF_decr_counter is
counter_decr_p_i : in std_logic; --! decrement enable
counter_load_i : in std_logic; --! load enable
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_zero_o : out std_logic --! empty counter indication
);
end entity WF_decr_counter;
......@@ -95,7 +95,7 @@ architecture rtl of WF_decr_counter is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -121,12 +121,12 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for the output signals
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
end architecture rtl;
--=================================================================================================
......
wf_engine_control.vhd
View file @ 297713da
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_engine_control.vhd
--! @file WF_engine_control.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
......@@ -20,7 +20,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- --
-- WF_engine_control --
-- --
......@@ -39,7 +39,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! ID_DAT frame structure :
--! ___________ ______ _______ ______ ___________ _______
--! |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__|
--!
--!
--!
--! Produced RP_DAT frame structure :
--! ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
......@@ -69,7 +69,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.04
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -87,19 +87,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! 07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG E0 added as broadcast \n
--! PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion;
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle;
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle;
--! state consume_wait_FSS, for the correct use of the silence time(time
--! stops counting when an RP_DAT frame has started)
--! 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode
--! stops counting when an RP_DAT frame has started)
--! 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode
--! for #bytes>4; in slone no broadcast
--! 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
--! assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
--! rx_byte_ready_p_o removed cleaning-up+commenting
--! 02/2011 v0.05 EG Independant timeout counter added; time counter 18 digits instead of 15
--! 02/2011 v0.05 EG Independant timeout counter added; time counter 18 digits instead of 15
--! id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_manch_ok_p not
--! activated
--
---------------------------------------------------------------------------------------------------
--
--! @todo -> could add an extra time counter (on top of the more complicated bytes counters) that
--! @todo -> could add an extra time counter (on top of the more complicated bytes counters) that
--! after 134*8 transmission periods can reset tx and rx
--!
---------------------------------------------------------------------------------------------------
......@@ -111,31 +113,31 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_engine_control is
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --!if negated,nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0);--! produced var user-data length
rate_i : in std_logic_vector (1 downto 0);--! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_fd_transmitter unit
tx_byte_request_p_i : in std_logic; --! used for the counting of the
tx_byte_request_p_i : in std_logic; --! used for the counting of the
--! # produced bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_fd_receiver unit
rx_byte_i : in std_logic_vector(7 downto 0);--!deserialized ID_DAT/ RP_DAT byte
......@@ -154,40 +156,40 @@ entity WF_engine_control is
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the WF_tx_serializer unit
tx_byte_request_accept_p_o : out std_logic;--! answer to tx_byte_request_p_i
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_p_o : out std_logic;--! launches the transmitters's FSM
tx_start_p_o : out std_logic;--! launches the transmitters's FSM
-- Signal to the WF_production unit
prod_data_lgth_o : out std_logic_vector (7 downto 0);--! # bytes of the Conrol & Data
--!fields of a prod RP_DAT frame
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_consumption
-- Signal to the WF_rx_deserializer
rx_rst_p_o : out std_logic;--!if a FES hasn't arrived after 8 bytes of an ID_DAT
--!or after 134 bytes of a RP_DAT, the state machine
--!of the WF_rx_deserializer returns to idle state
--!of the WF_rx_deserializer returns to idle state
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production & WF_consumption
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever
prod_cons_byte_index_o : out std_logic_vector (7 downto 0); --! index of the byte being
--! consumed/ produced
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production, WF_consumption, WF_reset_unit
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production, WF_consumption, WF_reset_unit
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever, WF_reset_unit
var_o : out t_var --! variable received by a valid ID_DAT frame
--! that concerns this station
--! that concerns this station
);
end entity WF_engine_control;
......@@ -207,11 +209,11 @@ architecture rtl of WF_engine_control is
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
signal s_load_time_counter, s_time_c_is_zero, s_session_timedout : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_byte_p, s_tx_last_byte_p_d : std_logic;
signal s_prod_data_lgth_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
......@@ -248,12 +250,12 @@ begin
--! it goes back to idle.
--! If the received variable is a consumed (var_1, var_2, var_rst) the FSM stays in the
--! "consume_wait_FSS" state until the arrival of a FSS or the expiration of the silence time.
--! After the arrival of a FSS the FSM jumps to the "consume" state, where it waits for the
--! After the arrival of a FSS the FSM jumps to the "consume" state, where it waits for the
--! WF_rx_deserializer to receive a FES.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
Engine_Control_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -265,14 +267,14 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Engine_Control_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_prod_or_cons,subs_i,
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_prod_or_cons,subs_i,
rx_crc_or_manch_wrong_p_i, s_session_timedout,
rx_fss_crc_fes_manch_ok_p_i, s_broadcast_var,
s_var_identified,rx_byte_ready_p_i,rx_byte_i,
s_var_identified,rx_byte_ready_p_i,rx_byte_i,
control_st, rx_fss_received_p_i,
s_rx_bytes_c, s_tx_last_byte_p)
......@@ -281,7 +283,7 @@ begin
case control_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle =>
if (rx_fss_received_p_i = '1') then -- correct FSS arrived
......@@ -292,10 +294,10 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_control_byte =>
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_control_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
elsif (rx_byte_ready_p_i = '1') then
......@@ -308,10 +310,10 @@ begin
nx_control_st <= id_dat_control_byte;-- ID_DAT Control byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_var_byte =>
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_var_byte =>
if (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
......@@ -326,9 +328,9 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte =>
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = subs_i) then
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber..
......@@ -349,19 +351,19 @@ begin
nx_control_st <= id_dat_subs_byte; -- ID_DAT subscriber byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok =>
if (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= produce_wait_turnar_time; -- CRC & FES check ok! station has to produce
nx_control_st <= produce_wait_turnar_time; -- CRC & FES check ok! station has to produce
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_prod_or_cons = "01") then
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then
nx_control_st <= idle; -- 3 bytes after the arrival of the subscriber
-- byte, a FES has not been detected
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= idle; -- byte, a FES has not been detected
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
......@@ -370,11 +372,11 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce_wait_turnar_time =>
if (s_time_c_is_zero = '1') then -- turnaround time passed
nx_control_st <= produce;
nx_control_st <= produce;
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
......@@ -384,29 +386,29 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume_wait_FSS =>
if (rx_fss_received_p_i = '1') then -- FSS of the consumed RP_DAT arrived
nx_control_st <= consume;
elsif (s_time_c_is_zero = '1') then -- if the FSS of the consumed RP_DAT frame doesn't
elsif (s_time_c_is_zero = '1') then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= idle; -- arrive before the expiration of the silence time,
-- the engine goes back to idle
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= consume_wait_FSS;-- counting silence time
end if;
nx_control_st <= consume_wait_FSS;-- counting silence time
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume =>
if (rx_fss_crc_fes_manch_ok_p_i = '1') or -- the cons frame arrived to the end,as expected
(rx_crc_or_manch_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(rx_crc_or_manch_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
nx_control_st <= idle; -- back to idle
......@@ -419,7 +421,7 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce =>
if (s_tx_last_byte_p = '1') then -- last byte to be produced
......@@ -433,13 +435,13 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
nx_control_st <= idle;
end case;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Engine_Control_FSM_Comb_Output_Signals : definition of the output
--! signals of the FSM
......@@ -464,7 +466,7 @@ begin
when id_dat_control_byte =>
s_idle_state <= '0';
---------------------------------
s_id_dat_ctrl_byte <= '1';
......@@ -478,7 +480,7 @@ begin
s_producing <= '0';
when id_dat_var_byte =>
when id_dat_var_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -508,7 +510,7 @@ begin
s_producing <= '0';
when id_dat_frame_ok =>
when id_dat_frame_ok =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -523,7 +525,7 @@ begin
s_producing <= '0';
when produce_wait_turnar_time =>
when produce_wait_turnar_time =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -583,7 +585,7 @@ begin
---------------------------------
when others =>
when others =>
---------------------------------
s_idle_state <= '1';
......@@ -597,7 +599,7 @@ begin
s_consuming <= '0';
s_producing <= '0';
end case;
end case;
end process;
......@@ -606,14 +608,14 @@ begin
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of the WF_prod_data_lgth_calc unit that calculates the total amount of
--! bytes that have to be transferred when a variable is produced (including the RP_DAT.Control,
--! RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes).
Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
port map (
slone_i => slone_i,
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
var_i => s_var,
......@@ -621,7 +623,7 @@ begin
prod_data_lgth_o => s_prod_data_lgth);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of the bytes that are
--! being produced. The counter is reset at the "produce_wait_turnar_time" state of the FSM and
--! counts bytes following the "tx_byte_request_p_i" pulse in the "produce" state.
......@@ -634,15 +636,15 @@ begin
incr_counter_i => s_inc_prod_bytes_counter,
-------------------------------------------------------
counter_o => s_prod_bytes_c,
counter_is_full_o => open );
counter_is_full_o => open );
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- when s_prod_data_lgth bytes have been counted,the signal s_prod_data_lgth_match is activated
s_prod_data_lgth_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_lgth) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of bytes that are
--! being received by the WF_rx_deserializer unit. The same counter is used for the bytes of an
--! ID_DAT frame or a consumed RP_DAT frame (that is why the name of the counter is s_rx_bytes_c
......@@ -665,9 +667,9 @@ begin
counter_is_full_o => open);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Combinatorial process Arguments_For_Both_Bytes_Counters: The process gives values to
--! the signals reinit_counter_i and incr_counter_i of the Produced_Bytes_Counter and
--! the signals reinit_counter_i and incr_counter_i of the Produced_Bytes_Counter and
--! Rx_Bytes_Counter according to the state of the FSM.
Arguments_For_Both_Bytes_Counters: process (s_id_dat_frame_ok, s_consuming, tx_byte_request_p_i,
......@@ -681,8 +683,8 @@ begin
s_rst_rx_bytes_counter <= '0';
s_inc_rx_bytes_counter <= rx_byte_ready_p_i;
s_rx_byte_index <= (others => '0');
s_rx_byte_index <= (others => '0');
elsif s_consuming = '1' then
s_rst_prod_bytes_counter <= '1';
......@@ -697,7 +699,7 @@ begin
elsif s_producing = '1' then
s_rst_rx_bytes_counter <= '1';
s_inc_rx_bytes_counter <= '0';
s_rx_byte_index <= (others => '0');
s_rx_byte_index <= (others => '0');
s_rst_prod_bytes_counter <= '0';
s_inc_prod_bytes_counter <= tx_byte_request_p_i;
......@@ -711,7 +713,7 @@ begin
s_rst_rx_bytes_counter <= '1';
s_inc_rx_bytes_counter <= '0';
s_rx_byte_index <= (others => '0');
s_rx_byte_index <= (others => '0');
end if;
end process;
......@@ -765,18 +767,18 @@ begin
-------------------------------------------------------
counter_is_zero_o => s_time_c_is_zero);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_package unit.
-- c_TIMEOUTS_TABLE declared in the WF_package unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Combinatorial process Turnaround_and_Silence_Time_Counter_Arg: The process gives values
--! to the counter_top and counter_load_i inputs of the Turnaround_and_Silence_Time_Counter,
--! according to the state of the FSM and the type of received variable (s_prod_or_cons).
......@@ -820,16 +822,16 @@ begin
--! o internal signal s_var_aux that locks to the value of the ID_DAT.Identifier.Variable byte
--! after its arrival
--! o output signal var_o (or s_var, used also internally by the WF_prod_data_lgth_calc) that
--! locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
--! locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
--! valid ID_DAT frame, if the specified station address concerns the station.
--! For a produced var this takes place at the "produce_wait_turnar_time" state, and
--! For a produced var this takes place at the "produce_wait_turnar_time" state, and
--! for a consumed at the "consume" state (not in the "consume_wait_silence_time", as at this
--! state it is not sure that a consumed RP_DAT frame will finally arrive).
--! state it is not sure that a consumed RP_DAT frame will finally arrive).
ID_DAT_var: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if nfip_rst_i = '1' then
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
......@@ -838,7 +840,7 @@ begin
-------------------------------------------------------------------------------------------
if (s_idle_state = '1') or (s_id_dat_ctrl_byte = '1') then -- new frame initializations
s_var_aux <= var_whatever;
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
......@@ -893,8 +895,8 @@ begin
-------------------------------------------------------------------------------------------
elsif (s_prod_wait_turnar_time = '1') or (s_consuming = '1') then -- ID_DAT OK!
s_var <= s_var_aux;
s_var <= s_var_aux;
end if;
end if;
......@@ -902,15 +904,15 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (needed by the FSM)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (needed by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue
else '0';
......@@ -919,7 +921,7 @@ begin
-- Introducing delays --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Registering the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_p_o
process (uclk_i)
......@@ -951,7 +953,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Concurrent Signal Assignments --
---------------------------------------------------------------------------------------------------
-- variable received by a valid ID_DAT frame that concerns this station
-- variable received by a valid ID_DAT frame that concerns this station
var_o <= s_var;
-- number of bytes of the Control & Data fields of a produced RP_DAT frame
......@@ -965,8 +967,8 @@ begin
-- If the WF_rx_deserializer continues receiving bytes when the engine_control is idle, it has to
-- be reset. This happens when the number of bytes that have arrived exceed the expected (ID_DAT >8
-- bytes and consumed RP_DAT > 130 bytes)
rx_rst_p_o <= s_idle_state and rx_byte_ready_p_i;
-- bytes and consumed RP_DAT > 130 bytes)
rx_rst_p_o <= s_idle_state and rx_byte_ready_p_i;
-- Production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
......
wf_fd_receiver.vhd
View file @ 297713da
......@@ -10,7 +10,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -37,7 +37,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_rx_osc : for the clock recovery
--!
--! o WF_rx_deglitcher : for the filtering of the input FD_RXD
--!
--!
--!
--! _________________________ _________________________
--! | | | |
......@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--! 0_____________________________FIELDBUS______________________________O
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -74,7 +74,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -83,17 +83,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--! ->
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -103,11 +103,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_fd_receiver is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHZ clock
-- nanoFIP WorldFIP Settings
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- nanoFIP FIELDRIVE
......@@ -122,17 +122,17 @@ entity WF_fd_receiver is
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- OUTPUTS
-- OUTPUTS
-- Signals to the WF_engine_control and WF_consumption
rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte
rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte
rx_fss_crc_fes_manch_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
-- Signals to the WF_engine_control
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP)
-- Signal to the WF_engine_control and the WF_production units
-- Signal to the WF_engine_control and the WF_production units
rx_crc_or_manch_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on
--!a ID_DAT or RP_DAT;pulse after the FES detection
);
......@@ -153,7 +153,7 @@ architecture struc of WF_fd_receiver is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
......@@ -164,7 +164,7 @@ begin
--! @brief Instantiation of the WF_rx_deglitcher unit.
FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher
FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -181,7 +181,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_osc unit.
......@@ -203,11 +203,11 @@ begin
---------------------------------------------------------------------------------------------------
-- Deserializer --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deserializer unit.
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -229,7 +229,7 @@ begin
------------------------------------------------------
end architecture struc;
--=================================================================================================
......@@ -237,4 +237,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_fd_transmitter.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -33,14 +33,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_tx_serializer : that receives bytes from the WF_Production, encodes them
--! (Manchester 2), adds the FSS, FCS & FES fields and puts one
--! by one bits to the FIELDRIVE output FD_TXD, following the
--! synchronization signals from the WF_tx_osc unit.
--! Also generates the nanoFIP output FD_TXENA.
--! synchronization signals from the WF_tx_osc unit.
--! Also generates the nanoFIP output FD_TXENA.
--!
--! o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK
--! and the array of pulses tx_clk_p_buff (used for the
--! synchronization of the WF_tx_serializer).
--! synchronization of the WF_tx_serializer).
--! ___________________________________________________________
--! | |
--! | |
--! | WF_Production |
--! |___________________________________________________________|
--! \/
......@@ -60,7 +60,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--! 0_____________________________FIELDBUS______________________________O
--!
--!
--!
......@@ -76,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -89,14 +89,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--! ->
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -107,7 +107,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_fd_transmitter is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; --! 40 MHz clock
......@@ -118,10 +118,10 @@ entity WF_fd_transmitter is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_production unit
tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production
......@@ -146,11 +146,11 @@ architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
......@@ -160,9 +160,9 @@ begin
--!@brief Instantiation of the WF_tx_osc unit
tx_oscillator: WF_tx_osc
tx_oscillator: WF_tx_osc
port map (
uclk_i => uclk_i,
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
......@@ -175,11 +175,11 @@ begin
---------------------------------------------------------------------------------------------------
-- Serializer --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_tx_serializer unit
tx_serializer: WF_tx_serializer
tx_serializer: WF_tx_serializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......
wf_incr_counter.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -37,24 +37,24 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 01/2011 EG v0.011 counter_full became a constant
--! -> 01/2011 EG v0.011 counter_full became a constant
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -62,22 +62,22 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity WF_incr_counter is
generic (g_counter_lgth : natural := 4); --! default length
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signals from any unit
incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned(g_counter_lgth-1 downto 0); --! counter
counter_is_full_o : out std_logic --! counter full indication
); --! (all bits to '1')
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_full_o : out std_logic --! counter full indication
); --! (all bits to '1')
end entity WF_incr_counter;
......@@ -90,14 +90,13 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
......@@ -114,7 +113,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
......
wf_manch_code_viol_check.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -41,13 +41,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! sampling is that of the half-bit-clock.
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition (the period is the double of the manch. sampling)
--! before the transition (the period is the double of the manch. sampling)
--!
--! Example:
--! bits : 0 1
--! bits : 0 1
--! manch. encoded : __|-- --|__
--! significant edge : ^ ^
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--
--
......@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.02
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -71,17 +71,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/12/2010 v0.02 EG cleaning-up+commenting
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -90,8 +90,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_rx_manch_code_check is
port (
-- INPUTS
-- nanoFIP User Interface general signal
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
......@@ -100,9 +100,9 @@ entity WF_rx_manch_code_check is
-- Signals from the WF_rx_deglitcher unit
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
serial_input_signal_i : in std_logic; --! input signal
serial_input_signal_i : in std_logic; --! input signal
-- OUTPUTS
-- Signal to the WF_rx_deserializer unit
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
......@@ -120,7 +120,7 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -130,13 +130,13 @@ begin
--! A violation exists if the signal and its delayed version are identical on the
--! check_code_viol_p moments.
-- 0 V- 1
-- rxd_filtered : __|--|____|--|__
-- rxd_filtered : __|--|____|--|__
-- serial_input_signal_d : __|--|____|--|__
-- check_code_viol : ^ ^ ^
Check_code_violations: process (uclk_i)
begin
if rising_edge (uclk_i) then
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0';
......@@ -146,7 +146,7 @@ begin
else
if sample_manch_bit_p_i = '1' then
s_serial_input_signal_d <= serial_input_signal_i;
s_serial_input_signal_d <= serial_input_signal_i;
end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
......@@ -154,15 +154,15 @@ begin
s_sample_bit_p_d1 <= sample_bit_p_i;
end if;
end if;
end process;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment
manch_code_viol_p_o <= s_check_code_viol_p and
manch_code_viol_p_o <= s_check_code_viol_p and
(not (serial_input_signal_i xor s_serial_input_signal_d));
end architecture rtl;
--=================================================================================================
......
wf_model_constr_decoder.vhd
View file @ 297713da
......@@ -29,7 +29,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
--! The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
--! is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0').
--! is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0').
--! Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd,
--! S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and
--! Constructor words take a value, according to the table: Gnd 00
......@@ -47,7 +47,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details\n
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -62,7 +62,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 PAS First version \n
--! -> 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
--! "for" loop replaced with signals concatenation;
--! "for" loop replaced with signals concatenation;
--! Counter is of c_RELOAD_MID_CID bits; Code cleaned-up \n
--! -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
--! counter unit instantiated
......@@ -70,8 +70,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! -> select_id_o not the output of a dff:-s
--! @todo
--! -> select_id_o not the output of a dff:-s
--
---------------------------------------------------------------------------------------------------
......@@ -83,7 +83,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_model_constr_decoder is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock
......@@ -114,7 +114,7 @@ architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
......@@ -144,7 +144,7 @@ begin
s_constr_stage2 <= (others => '0');
else
s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage1 <= model_id_i; -- and stage2 the odd ones
......@@ -154,12 +154,12 @@ begin
if s_counter = "10" then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits
s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0);
constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) &
constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) &
s_constr_stage2(2) & s_constr_stage1(2) &
s_constr_stage2(1) & s_constr_stage1(1) &
s_constr_stage2(0) & s_constr_stage1(0);
......@@ -183,13 +183,13 @@ begin
counter_o => s_counter,
counter_is_full_o => s_counter_is_full);
-----------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignment for the output select_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using
-- the LSB of the counter
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
......
wf_package.vhd
View file @ 297713da
......@@ -35,7 +35,7 @@ use ieee.numeric_std.all;
--! @version v0.04
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--
......@@ -43,22 +43,22 @@ use ieee.numeric_std.all;
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) \n
--! -> 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
--! -> 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
--! std_logic_vector(9 downto 0) to simplify calculations; cleaning-up
--! -> 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--! -> 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--! added DualClkRam
--! -> 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -79,12 +79,9 @@ package WF_package is
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculation --
---------------------------------------------------------------------------------------------------
constant c_CRC_GENER_POLY_LGTH : natural := 16;
constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) :=
"0001110111001111";
constant c_CRC_VERIFIC_MASK : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) :=
"0001110001101011";
constant c_CRC_POLY_LGTH : natural := 16;
constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110111001111";
constant c_CRC_VERIF_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110001101011";
---------------------------------------------------------------------------------------------------
......@@ -98,7 +95,7 @@ package WF_package is
constant c_PRE : std_logic_vector (15 downto 0) := c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
constant c_FES : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
constant c_FES : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
constant c_FSS : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
......@@ -112,17 +109,17 @@ package WF_package is
constant c_PROD_CONS_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
---------------------------------------------------------------------------------------------------
-- Constants regarding the nanoFIP status bits --
---------------------------------------------------------------------------------------------------
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_TLER_INDEX : integer := 4;
constant c_R_FCSER_INDEX : integer := 5;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_TLER_INDEX : integer := 4;
constant c_R_FCSER_INDEX : integer := 5;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
......@@ -139,7 +136,7 @@ package WF_package is
---------------------------------------------------------------------------------------------------
constant c_TX_CLK_BUFF_LGTH : natural := 4; -- length of the clk buffer used for
-- the transmission synchronization
-- the transmission synchronization
......@@ -147,8 +144,8 @@ package WF_package is
-- Constants regarding the MPS status bits --
---------------------------------------------------------------------------------------------------
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
......@@ -160,7 +157,7 @@ package WF_package is
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
......@@ -174,14 +171,14 @@ package WF_package is
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(7 downto 0) :=
constant c_P3_LGTH_TABLE : t_unsigned_array(7 downto 0) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010"); -- reserved
others => "00000010"); -- reserved
......@@ -191,13 +188,13 @@ package WF_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- bits is the max needed for counting
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
......@@ -223,33 +220,33 @@ package WF_package is
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
type t_timeouts is
type t_timeouts is
record
turnaround : integer;
silence : integer;
end record;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_RESERVE_INDEX : integer := 3;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_RESERVE_INDEX : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD),
silence => integer (100000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (5160000.0 /C_QUARTZ_PERIOD)));
---------------------------------------------------------------------------------------------------
......@@ -273,7 +270,7 @@ package WF_package is
end record;
type t_var_array is array (natural range <>) of t_var_record;
constant c_VAR_PRESENCE_INDEX : integer := 0;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
......@@ -282,20 +279,20 @@ package WF_package is
constant c_VAR_RST_INDEX : integer := 5;
constant c_VARS_ARRAY : t_var_array(0 to 5) :=
constant c_VARS_ARRAY : t_var_array(0 to 5) :=
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
hexvalue => x"14",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0;-))
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
7 => x"00", others => x"ff")),
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
prod_or_cons => "10",
......@@ -307,9 +304,9 @@ package WF_package is
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
others => x"ff")),
c_VAR_3_INDEX => (var => var_3,
hexvalue => x"06",
hexvalue => x"06",
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
......@@ -320,7 +317,7 @@ package WF_package is
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
hexvalue => x"05",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
......@@ -336,17 +333,17 @@ package WF_package is
broadcast => '1',
base_addr => "010000000",
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
hexvalue => x"e0",
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")));
......@@ -358,7 +355,7 @@ package WF_package is
---------------------------------------------------------------------------------------------------
component WF_rx_deserializer
component WF_rx_deserializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
......@@ -368,15 +365,15 @@ package WF_package is
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
fd_rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
-----------------------------------------------------------------
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
crc_or_manch_wrong_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rx_osc_rst_o : out std_logic);
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_deserializer;
......@@ -384,33 +381,33 @@ package WF_package is
---------------------------------------------------------------------------------------------------
component WF_tx_serializer
component WF_tx_serializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
tx_start_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
-----------------------------------------------------------------
-----------------------------------------------------------------
byte_request_p_o : out std_logic;
tx_osc_rst_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
-----------------------------------------------------------------
end component WF_tx_serializer;
---------------------------------------------------------------------------------------------------
component WF_cons_bytes_processor
component WF_cons_bytes_processor
port (
uclk_i : in std_logic;
slone_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
......@@ -418,7 +415,7 @@ package WF_package is
-----------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0));
......@@ -432,16 +429,16 @@ package WF_package is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
subs_i : in std_logic_vector (7 downto 0);
nfip_rst_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
wb_clk_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
......@@ -477,9 +474,9 @@ package WF_package is
component WF_rx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_edge_p_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_edge_p_i : in std_logic;
rx_osc_rst_i : in std_logic;
-----------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
......@@ -498,13 +495,13 @@ end component WF_rx_osc;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
wb_ack_prod_p_i : in std_logic;
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
......@@ -543,7 +540,7 @@ end component WF_rx_osc;
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
end component WF_fd_transmitter;
......@@ -556,7 +553,7 @@ end component WF_rx_osc;
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_osc_rst_p_i : in std_logic;
tx_osc_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0));
......@@ -568,16 +565,16 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_prod_bytes_retriever is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_ack_prod_p_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
......@@ -586,30 +583,30 @@ end component WF_rx_osc;
byte_index_i : in std_logic_vector (7 downto 0);
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
-----------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
-----------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_bytes_retriever;
---------------------------------------------------------------------------------------------------
component WF_engine_control
---------------------------------------------------------------------------------------------------
component WF_engine_control
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_byte_request_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_accept_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
......@@ -623,23 +620,22 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_reset_unit
---------------------------------------------------------------------------------------------------
component WF_reset_unit
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
wb_clk_i : in std_logic;
rstin_a_i : in std_logic;
rstpon_i : in std_logic;
rstin_a_i : in std_logic;
rstpon_a_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
var_i : in t_var;
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-----------------------------------------------------------------
wb_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
rston_o : out std_logic;
fd_rstn_o : out std_logic);
fd_rstn_o : out std_logic);
-----------------------------------------------------------------
end component WF_reset_unit;
......@@ -647,10 +643,10 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_DualClkRAM_clka_rd_clkb_wr
generic (g_ram_data_lgth : integer;
g_ram_addr_lgth : integer);
generic (g_ram_data_lgth : integer;
g_ram_addr_lgth : integer);
port (
clk_porta_i : in std_logic;
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
......@@ -659,32 +655,32 @@ end component WF_rx_osc;
-----------------------------------------------------------------
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0));
-----------------------------------------------------------------
end component WF_DualClkRAM_clka_rd_clkb_wr;
end component WF_DualClkRAM_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component DualClkRam is
component DualClkRam is
port (
CLKA : in std_logic;
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
-----------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0));
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
-----------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component DualClkRam;
---------------------------------------------------------------------------------------------------
component WF_crc
component WF_crc
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
......@@ -692,8 +688,8 @@ end component WF_rx_osc;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
-----------------------------------------------------------------
crc_ok_p_o : out std_logic;
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0));
crc_ok_p_o : out std_logic;
crc_o : out std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0));
-----------------------------------------------------------------
end component WF_crc;
......@@ -703,8 +699,8 @@ end component WF_rx_osc;
component WF_manch_encoder is
generic (g_word_lgth : natural);
port (
word_i : in std_logic_vector (g_word_lgth-1 downto 0);
-----------------------------------------------------------------
word_i : in std_logic_vector (g_word_lgth-1 downto 0);
-----------------------------------------------------------------
word_manch_o : out std_logic_vector ((2*g_word_lgth)-1 downto 0));
-----------------------------------------------------------------
end component WF_manch_encoder;
......@@ -715,26 +711,26 @@ end component WF_rx_osc;
component WF_rx_manch_code_check is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
nfip_rst_i : in std_logic;
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
-----------------------------------------------------------------
manch_code_viol_p_o : out std_logic);
manch_code_viol_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_manch_code_check;
---------------------------------------------------------------------------------------------------
component WF_rx_deglitcher
component WF_rx_deglitcher
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
nfip_rst_i : in std_logic;
fd_rxd_a_i : in std_logic;
-----------------------------------------------------------------
fd_rxd_filtered_o : out std_logic;
fd_rxd_filtered_edge_p_o : out std_logic;
fd_rxd_filtered_edge_p_o : out std_logic;
fd_rxd_filtered_f_edge_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_deglitcher;
......@@ -742,28 +738,28 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_status_bytes_gen
component WF_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_p_i : in std_logic;
-----------------------------------------------------------------
-----------------------------------------------------------------
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_status_bytes_gen;
......@@ -773,8 +769,8 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_bits_to_txd
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
txd_bit_index_i : in unsigned (4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
......@@ -795,42 +791,42 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component nanofip
port (
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
rstin_i : in std_logic;
rstin_i : in std_logic;
rstpon_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
wb_clk_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
wb_clk_i : in std_logic;
dat_i : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector (9 downto 0);
adr_i : in std_logic_vector (9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
-----------------------------------------------------------------
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
we_i : in std_logic;
-----------------------------------------------------------------
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
ack_o : out std_logic;
......@@ -841,16 +837,16 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_model_constr_decoder
component WF_model_constr_decoder
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
-----------------------------------------------------------------
select_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0));
select_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_model_constr_decoder;
......@@ -877,7 +873,7 @@ end component WF_rx_osc;
component WF_incr_counter is
generic (g_counter_lgth : natural := 8);
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
reinit_counter_i : in std_logic;
incr_counter_i : in std_logic;
-----------------------------------------------------------------
......@@ -891,12 +887,12 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_prod_data_lgth_calc is
port (
slone_i : in std_logic;
nostat_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
-----------------------------------------------------------------
prod_data_lgth_o : out std_logic_vector (7 downto 0));
prod_data_lgth_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_data_lgth_calc;
......@@ -905,17 +901,17 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_cons_outcome is
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
nfip_rst_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
var_i : in t_var;
rx_byte_index_i : in std_logic_vector (7 downto 0);
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
......@@ -923,7 +919,7 @@ end component WF_rx_osc;
var2_rdy_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic);
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_cons_outcome;
......@@ -932,9 +928,9 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_prod_permit is
port (
uclk_i : in std_logic;
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
var_i : in t_var;
-----------------------------------------------------------------
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
......@@ -945,22 +941,22 @@ end component WF_prod_permit;
---------------------------------------------------------------------------------------------------
component WF_wb_controller is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_id_i : in std_logic_vector (2 downto 0);
-----------------------------------------------------------------
wb_ack_prod_p_o : out std_logic;
wb_ack_p_o : out std_logic);
wb_ack_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_wb_controller;
---------------------------------------------------------------------------------------------------
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
......@@ -975,7 +971,7 @@ package body WF_package is
---------------------------------------------------------------------------------------------------
--!@brief Function for the encoding of a word to its Manchester 2 (manch.) equivalent.
--! Each bit "1" is replaced by "10" and each bit "0" by "01".
--! Each bit "1" is replaced by "10" and each bit "0" by "01".
--! The manch. encoding ensures that there is one transition for each bit.
--! o bit : "0" "1"
--! o manch. encoded : "0 1" "1 0"
......@@ -984,7 +980,7 @@ package body WF_package is
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector ((2*word_i'length) -1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
......
wf_prod_bytes_retriever.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -27,8 +27,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief After an ID_DAT frame requesting for a variable to be produced, the unit provides
--! to the WF_tx_serializer unit one by one, \n all the bytes of data needed for the
--! @brief After an ID_DAT frame requesting for a variable to be produced, the unit provides
--! to the WF_tx_serializer unit one by one, \n all the bytes of data needed for the
--! RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the
--! retreival is done through the WF_engine_control and the signal byte_index_i.
--!
......@@ -37,16 +37,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__||____FCS____|__FES__|
--!
--! Data provided by the this unit :
--! ______ _______ ______ ________________________________________ _______ _______
--! ______ _______ ______ ________________________________________ _______ _______
--! |_Ctrl_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__||
--!
--! If the variable to be produced is the
--! o presence : the unit retreives the bytes from the WF_package.
--! Note: No MPS & no nanoFIP status associated with this variable.
--! ______ _______ ______ ______ ______ ______ ______ ______
--! ______ _______ ______ ______ ______ ______ ______ ______
--! |_Ctrl_||__PDU__|__05__|__80__|__03__|__00__|__F0__|__00__||
--!
--!
--!
--! o identification : the unit retreives the Constructor & Model bytes from the
--! WF_model_constr_decoder, and all the rest from the WF_package.
--! Note: No MPS & no nanoFIP status associated with this variable.
......@@ -63,7 +63,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_status_bytes_gen, and the LGTH byte from the
--! WF_prod_data_lgth_calc (inside the WF_engine_control). The
--! rest of the bytes (Ctrl & PDU) come from the WF_package.
--! ______ _______ ______ ________________________________________ _______ _______
--! ______ _______ ______ ________________________________________ _______ _______
--! |_Ctrl_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__||
--
--
......@@ -77,7 +77,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.05
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -87,14 +87,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_status_bytes_gen \n
--! WF_model_constr_dec \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! \n\n<b>Last changes:</b>\n
--! -> 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
--! -> 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
--! signal s_wb_we includes the wb_stb_r_edge_p_i
--! cleaner structure
--! -> 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it
......@@ -109,10 +109,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -123,15 +123,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_prod_bytes_retriever is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
......@@ -157,14 +157,14 @@ entity WF_prod_bytes_retriever is
-- 1 byte RP_DAT.Data.LENGTH
-- 2-124 bytes of RP_DAT.Data,
-- 1 byte RP_DAT.Data.MPS_status &
-- optionally 1 byte for the
-- RP_DAT.Data.nanoFIP_status
-- optionally 1 byte for the
-- RP_DAT.Data.nanoFIP_status
var_i : in t_var; --!variable type that is being treated
-- Signals from the WF_prod_permit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from the WF_prod_permit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from the WF_status_bytes_gen
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
......@@ -196,31 +196,31 @@ architecture rtl of WF_prod_bytes_retriever is
signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0);
signal s_byte_index_d_aux : integer range 0 to 15;
signal s_lgth_byte, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index_d : std_logic_vector (7 downto 0);
signal s_byte_index_d : std_logic_vector (7 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Produced RAM --
-- Storage (by the user) & retreival (by the unit) of produced bytes --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a Produced Dual Port RAM.
--! Port A is used by the nanoFIP for the readings from the Produced RSM;
--! Port B is connected to the WISHBONE interface for the writings from the user.
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- remaining 7 : address of a byte inside the blck
port map (
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
......@@ -230,7 +230,7 @@ begin
write_en_portb_i => wb_ack_prod_p_i, -- WISHBONE write enable
-----------------------------------------
data_porta_o => s_mem_byte); -- output byte read
-----------------------------------------
-----------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -240,24 +240,24 @@ begin
--!@brief Sampling of the input data bus DAT_I(15:0) for the operation in stand-alone mode.
--! The sampling takes place on the 1st clock cycle after the VAR3_RDY has been de-asserted.
Sample_DAT_I_bus: process (uclk_i)
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge (uclk_i) then
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_sampled_data <= (others=>'0');
else
else
if var3_rdy_i = '1' then -- data latching
s_sampled_data <= slone_data_i;
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_slone_byte <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
else s_sampled_data(15 downto 8);
......@@ -265,63 +265,63 @@ begin
-- Bytes Generation --
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data
--! fields of an RP_DAT frame:\n If the variable requested in the ID_DAT is of "produced" type
--! fields of an RP_DAT frame:\n If the variable requested in the ID_DAT is of "produced" type
--! (identification/ presence/ var3) the process prepares accordingly, one by one, bytes of data
--! to be sent. \n The pointer "s_byte_index_d" (or "s_byte_index_d_aux") indicates which byte of the
--! frame is to be sent. Some of the bytes are defined in the WF_package, the rest come either from
--! to be sent. \n The pointer "s_byte_index_d" (or "s_byte_index_d_aux") indicates which byte of the
--! frame is to be sent. Some of the bytes are defined in the WF_package, the rest come either from
--! the memory (if slone = 0) or from the the input bus data_i (if slone = 1) or from the
--! WF_status_bytes_gen or the WF_model_constr_decoder units.\n The output byte "byte_o" is sent to
--! the WF_tx_serializer unit for manchester encoding and serialization.
Bytes_Generation: process (var_i, s_byte_index_d, data_lgth_i, constr_id_dec_i, model_id_dec_i,
Bytes_Generation: process (var_i, s_byte_index_d, data_lgth_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux,
s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i)
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- generation of bytes according to the type of produced var:
case var_i is
-- case: presence variable
-- case: presence variable
-- all the bytes for the RP_DAT.Control and RP_DAT.Data fields of the RP_DAT frame to be sent,
-- are predefined in the c_VARS_ARRAY matrix.
when var_presence =>
byte_o <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).byte_array(s_byte_index_d_aux);
s_base_addr <= (others => '0');
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_base_addr <= (others => '0');
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- case: identification variable
-- The Constructor and Model bytes of the identification variable arrive from the
-- WF_model_constr_decoder, wereas all the rest are predefined in the c_VARS_ARRAY matrix.
-- WF_model_constr_decoder, wereas all the rest are predefined in the c_VARS_ARRAY matrix.
when var_identif =>
if s_byte_index_d = c_CONSTR_BYTE_INDEX then
byte_o <= constr_id_dec_i;
if s_byte_index_d = c_CONSTR_BYTE_INDEX then
byte_o <= constr_id_dec_i;
elsif s_byte_index_d = c_MODEL_BYTE_INDEX then
byte_o <= model_id_dec_i;
elsif s_byte_index_d = c_MODEL_BYTE_INDEX then
byte_o <= model_id_dec_i;
else
byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_d_aux);
byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_d_aux);
end if;
s_base_addr <= (others => '0');
s_base_addr <= (others => '0');
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- case: variable 3 (06h)
-- For a var_3 there is a separation according to the operational mode (stand-alone or memory)
-- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, wereas the rest come
-- either from the memory/ data_i bus or from status_generator unit (WF_status_gen).
-- either from the memory/ data_i bus or from status_generator unit (WF_status_gen).
when var_3 =>
---------------------------------------------------------------------------------------------
......@@ -329,89 +329,89 @@ begin
if slone_i = '0' then
-- retreival of base address info for the memory from the WF_package
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr;
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux);
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The c_LGTH_BYTE_INDEX byte is the Length
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place)
-- (if nostat_i is not negated, the "else" condition takes place)
elsif (unsigned(s_byte_index_d) = (unsigned(data_lgth_i)-1 )) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status
elsif s_byte_index_d = (data_lgth_i) then
elsif s_byte_index_d = (data_lgth_i) then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent
-- The reset arrives after having sent
-- the MPS byte to the WF_tx_serializer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The rest of the bytes come from the memory
else
byte_o <= s_mem_byte;
rst_status_bytes_p_o <= '0';
byte_o <= s_mem_byte;
rst_status_bytes_p_o <= '0';
end if;
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- In stand-alone mode:
else
s_base_addr <= (others => '0'); -- no memory access needed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU type) bytes to be sent
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux);
rst_status_bytes_p_o <= '0';
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The c_LGTH_BYTE_INDEX byte is the Length
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place)
-- (if nostat_i is not negated, the "else" condition takes place)
elsif unsigned(s_byte_index_d) = (unsigned(data_lgth_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
elsif unsigned(s_byte_index_d) = (unsigned(data_lgth_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status
elsif s_byte_index_d = data_lgth_i then
elsif s_byte_index_d = data_lgth_i then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent the
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent the
-- MPS byte to the WF_tx_serializer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The rest of the bytes come from the input bus data_i(15:0)
else
byte_o <= s_slone_byte;
byte_o <= s_slone_byte;
rst_status_bytes_p_o <= '0';
end if;
......@@ -419,24 +419,24 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_1 | var_2 | var_rst | var_whatever =>
when var_1 | var_2 | var_rst | var_whatever =>
rst_status_bytes_p_o <= '0';
byte_o <= (others => '0');
s_base_addr <= (others => '0');
byte_o <= (others => '0');
s_base_addr <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
when others =>
rst_status_bytes_p_o <= '0';
byte_o <= (others => '0');
s_base_addr <= (others => '0');
end case;
byte_o <= (others => '0');
s_base_addr <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@briedf Synchronous process Delay_byte_index_i: in the combinatorial process Bytes_Generation,
--! according to the value of the signal s_byte_index_d, a byte is retrieved either from the memory,
--! or from the WF_package or from the WF_status_bytes_gen or WF_model_constr_decoder units.
......@@ -445,14 +445,14 @@ begin
--! (byte_index_i is the signal used as address for the mem; s_byte_index_d is the delayed one
--! used for the other units).
Delay_byte_index_i: process (uclk_i)
Delay_byte_index_i: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte_index_d <= (others => '0');
else
s_byte_index_d <= (others => '0');
else
s_byte_index_d <= byte_index_i; -- index of byte to be sent
s_byte_index_d <= byte_index_i; -- index of byte to be sent
end if;
end if;
end process;
......@@ -469,7 +469,7 @@ begin
-- memory (for example when byte_index_i is 3 which means that the Control, PDU_TYPE and Length
-- bytes have preceeded and a byte from the memory is now requested, the byte from the memory cell
-- 2 (00000010) has to be retrieved).
s_mem_addr_offset <= (resize((unsigned(byte_index_i)), s_mem_addr_offset'length));
s_byte_index_d_aux <= (to_integer(unsigned(s_byte_index_d(3 downto 0))));
......@@ -477,8 +477,8 @@ begin
-- used to retreive bytes from the matrix
-- c_VARS_ARRAY.byte_array, with a predefined
-- width of 15 bytes
s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length));
s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length));
-- represents the RP_DAT.Data.LENGTH byte
-- it includes the # bytes of user-data
-- (P3_LGTH) plus 1 byte of MPS_status
......
wf_prod_data_lgth_calc.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.02
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
......@@ -70,19 +70,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -93,7 +93,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- INPUTS
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
......@@ -123,15 +123,15 @@ architecture behavior of WF_prod_data_lgth_calc is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
--! FSS and before the FCS, that have to be transferred when a variable is produced. In the case
--! FSS and before the FCS, that have to be transferred when a variable is produced. In the case
--! of the presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin
......@@ -141,19 +141,19 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_3 =>
when var_3 =>
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced(independently of P3_LGTH)
......@@ -162,21 +162,21 @@ begin
-- 1 byte Length
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data
-- to these, there should be added 1 byte Control
-- 1 byte PDU_TYPE
-- 1 byte Length
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- optionally 1 byte nFIP status
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
else -- 7 bytes
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
else -- 7 bytes
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
end if;
......@@ -186,21 +186,21 @@ begin
else
s_prod_data_lgth <= s_p3_lgth_decoded + 3;
end if;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst =>
when var_1 | var_2 | var_rst =>
s_prod_data_lgth <= (others => '0');
when others =>
when others =>
s_prod_data_lgth <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
......
wf_prod_permit.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
--! according to the variable (var_i) that is being treated.
--! according to the variable (var_i) that is being treated.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
......@@ -51,16 +51,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 1/2011 v0.01 EG First version \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -71,7 +71,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_prod_permit is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
......@@ -97,11 +97,11 @@ architecture rtl of WF_prod_permit is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR3_RDY_Generation:
--!@brief Synchronous process VAR3_RDY_Generation:
--! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
--! memory or access the DAT_I bus. It is deasserted right after the end of the reception of a
......@@ -115,7 +115,7 @@ begin
--! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the
--! RP_DAT.data field;var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission).
VAR_RDY_Generation: process (uclk_i)
VAR_RDY_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -125,17 +125,17 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is
when var_3 => -- nanoFIP is producing
when var_3 => -- nanoFIP is producing
---------------------
var3_rdy_o <= '0'; -- while producing, VAR3_RDY is 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
var3_rdy_o <= '1';
end case;
var3_rdy_o <= '1';
end case;
end if;
end if;
end process;
......
wf_production.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -27,23 +27,23 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit groups the main actions that regard data production.
--! @brief The unit groups the main actions that regard data production.
--! It instantiates the units:
--!
--! o WF_prod_bytes_retriever: that retrieves
--! o user-data bytes: from the Produced RAM or the
--! "nanoFIP User Interface, NON-WISHBONE" bus DAT_I,
--! o PDU,Ctrl bytes : from the WF_package
--! "nanoFIP User Interface, NON-WISHBONE" bus DAT_I,
--! o PDU,Ctrl bytes : from the WF_package
--! o MPS,nFIP status: from the WF_status_bytes_gen
--! o LGTH byte : from the WF_prod_data_lgth_calc
--! and following the signals from the external unit
--! WF_engine_control forwards them to the WF_fd_transmitter
--! WF_engine_control forwards them to the WF_fd_transmitter
--!
--! o WF_status_bytes_gen : that receives information from the WF_consumption unit,
--! the "FIELDRIVE" and "User Interface,NON-WISHBONE"inputs
--! and outputs, for the generation of the nanoFIP & MPS
--! status bytes
--!
--! status bytes
--!
--! o WF_prod_permit : that signals the user that user-data bytes can safely be
--! written
--!
......@@ -63,15 +63,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | |
--! | |
--! | WF_fd_transmitter |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--! 0_____________________________FIELDBUS______________________________O
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
--! which of the instantiated units needs it.
--!
--
--
......@@ -85,7 +85,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.02
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -105,10 +105,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -119,7 +119,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_production is
port (
-- INPUTS
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
......@@ -128,7 +128,7 @@ entity WF_production is
slone_i : in std_logic;
-- used by: WF_prod_bytes_retriever for the selection of data bytes from the RAM or the DAT_I
-- used by: WF_status_bytes_gen because the MPS status is different in memory & stand-alone
-- used by: WF_status_bytes_gen because the MPS status is different in memory & stand-alone
nostat_i : in std_logic;
-- used by: WF_prod_bytes_retriever for the delivery or not of the nanoFIP status byte
......@@ -144,7 +144,7 @@ entity WF_production is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
-- used by: WF_prod_bytes_retriever for the managment of the Production RAM
......@@ -153,18 +153,18 @@ entity WF_production is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_wb_controller
wb_ack_prod_p_i : in std_logic;
wb_ack_prod_p_i : in std_logic;
-- used by: WF_prod_bytes_retriever for the latching of the wb_data_i
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);
-- used by: WF_prod_bytes_retriever for the bytes retreival in stand-alone mode
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
-- used by: WF_status_bytes_gen for the nanoFIP status byte, bits 2, 3
......@@ -194,10 +194,10 @@ entity WF_production is
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
-- used by: WF_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5
-- used by: WF_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_model_constr_decoder unit
constr_id_dec_i : in std_logic_vector (7 downto 0);
......@@ -229,17 +229,17 @@ end entity WF_production;
architecture struc of WF_production is
signal s_var3_rdy, s_rst_status_bytes_p : std_logic;
signal s_stat, s_mps : std_logic_vector (7 downto 0);
signal s_stat, s_mps : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Production Permit --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_prod_permit unit
......@@ -256,32 +256,32 @@ begin
---------------------------------------------------------------------------------------------------
-- Bytes Retreival --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_prod_bytes_retriever unit
production_bytes_retriever : WF_prod_bytes_retriever
port map (
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
constr_id_dec_i => constr_id_dec_i,
slone_i => slone_i,
nostat_i => nostat_i,
slone_i => slone_i,
nostat_i => nostat_i,
nfip_rst_i => nfip_rst_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
wb_ack_prod_p_i => wb_ack_prod_p_i,
nFIP_status_byte_i => s_stat,
nFIP_status_byte_i => s_stat,
mps_status_byte_i => s_mps,
var_i => var_i,
byte_index_i => byte_index_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_being_sent_p_i => byte_request_accept_p_i,
data_lgth_i => data_lgth_i,
data_lgth_i => data_lgth_i,
wb_data_i => wb_data_i,
slone_data_i => slone_data_i,
var3_rdy_i => s_var3_rdy,
-----------------------------------------------
rst_status_bytes_p_o => s_rst_status_bytes_p,
rst_status_bytes_p_o => s_rst_status_bytes_p,
byte_o => byte_o);
-----------------------------------------------
......@@ -289,11 +289,11 @@ begin
---------------------------------------------------------------------------------------------------
-- Status Byte Generation --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_status_bytes_gen unit
production_status_bytes_generator : WF_status_bytes_gen
production_status_bytes_generator : WF_status_bytes_gen
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......
wf_reset_unit.vhd
View file @ 297713da
......@@ -45,13 +45,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |__________| \ \
--! __________ | \
--! rst_nFIP_and_FD_p | | | | nFIP_rst
--! ________| FSM |________ |OR | _______________
--! ________| FSM |________ |OR | _______________
--! | var_rst | | |
--! |__________| | /
--! / /
--! RSTPON / /
--! __________________________ / /
--! / /
--! / /
--!
--!
--! o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN
......@@ -67,32 +67,31 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |__________| \ \
--! __________ | \
--! rst_nFIP_and_FD_p | | | | FD_RSTN
--! ________| FSM |________ |OR | _______________
--! ________| FSM |________ |OR | _______________
--! | var_rst | | |
--! |__________| | /
--! / /
--! RSTPON / /
--! __________________________ / /
--! / /
--!
--!
--! o reset to the external logic: nanoFIP User Interface, General signal RSTON
--! / /
--!--!
--! o reset to the external logic: nanoFIP User Interface, General signal RSTON
--! It is asserted after the reception of a valid var_rst with its 2nd data byte
--! containing the station's address. It stays active for 8 uclk cycles.
--! __________
--! assert_RSTON | | RSTON
--! ________| FSM |_________________________________
--! | var_rst |
--! |__________|
--!
--! _________
--! assert_RSTON_p | | RSTON
--! ________| FSM |_________________________________
--! | var_rst |
--! |__________|
--!
--!
--! o nanoFIP internal reset for the WISHBONE logic:
--! o nanoFIP internal reset for the WISHBONE logic:
--! It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE
--! Slave" input RST_I (not synchronized, to comply with with WISHBONE rule 3.15)
--! or of the "nanoFIP User Interface General signal" RSTPON.
--! It stays asserted for as long as the RST_I or RSTPON stay asserted.
--!
--! RSTPON
--!
--! RSTPON
--! __________________________ \ \
--! \ \ wb_rst
--! RST_I |OR|____________________
......@@ -105,18 +104,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! only after the sucessful validation of the frame structure and of the application-
--! data bytes of a var_rst; in this unit they are used here directly,
--! without any handling.
--! o The Power On Reset signal is used directly, without any handling.
--! o The Power On Reset signal is used directly, without any handling.
--! --->>Still missing the synchronization with the uclk and wb_clk of the falling edge
-- of RSTPON
--!
--! The unit implements 2 state machines: one for resets coming from RSTIN
--! and one for resets coming from a var_rst.
--!
--!
--!
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch) \n
......@@ -130,11 +126,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details
--! @details
--
--! \n<b>Dependencies:</b> \n
--! WF_cons_bytes_processor \n
--
--
--
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
......@@ -148,12 +144,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for>4 uclk
--! 01/2011 v0.03 EG PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs
--! treated in the wf_cons_outcome; 2 state machines created; clean-up
--! PoR also for internal WISHBONE resets
--! PoR also for internal WISHBONE resets
--
---------------------------------------------------------------------------------------------------
--
--! @todo -> synchronize falling edge (@ deactivation) of asynchronous RSTPON to uclk and wb_clk
--! here for the moment we just use rstpon_i for both worlds
--! here for the moment we just use rstpon_a_i for both worlds
--
---------------------------------------------------------------------------------------------------
......@@ -165,20 +161,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_reset_unit is
port (
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; --! 40 MHz clock
rstin_a_i : in std_logic; --! initialisation control, active low (synch/ed with uclk)
rstpon_i : in std_logic; --! Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate (synch/ed with uclk)
wb_clk_i : in std_logic;
-- nanoFIP User Interface General signals
uclk_i : in std_logic; --! 40 MHz clock
rstin_a_i : in std_logic; --! initialization control, active low
rstpon_a_i : in std_logic; --! Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- nanoFIP User Interface WISHBONE Slave
rst_i : in std_logic; --! WISHBONE reset
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
wb_clk_i : in std_logic; --! WISHBONE clock
-- Signal from the WF_consumption unit
rst_nFIP_and_FD_p_i : in std_logic; --! indicates that a var_rst with its 1st byte
......@@ -198,7 +189,7 @@ entity WF_reset_unit is
-- Signal to the WF_wb_controller
wb_rst_o : out std_logic; --! reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
-- nanoFIP User Interface General signal output
rston_o : out std_logic; --! reset output, active low
-- nanoFIP FIELDRIVE output
......@@ -212,29 +203,27 @@ end entity WF_reset_unit;
--=================================================================================================
architecture rtl of WF_reset_unit is
signal s_counter_is_four, s_reinit_counter, s_rston, s_FD_rst_from_var_rst : std_logic;
type rstin_st_t is (idle, rstin_eval, nfip_on_fd_on, nfip_off_fd_on);
type var_rst_st_t is (var_rst_idle, var_rst_rston_on, var_rst_nfip_on_fd_on_rston_on,
var_rst_nfip_off_fd_on_rston_on, var_rst_nfip_on_fd_on,
var_rst_nfip_off_fd_on_rston_off);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
signal rstin_st, nx_rstin_st : rstin_st_t;
signal s_counter_is_four, s_reinit_counter, s_rston, s_var_rst_fd_rst : std_logic;
signal s_u_por_ff1, s_u_por, s_wb_por_ff1, s_wb_por : std_logic;
signal s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst, s_fd_rst_from_RSTIN : std_logic;
signal s_counter_is_ten, s_counter_is_full, s_counter_full : std_logic;
signal s_rstin_nfip_rst, s_var_rst_nfip_rst, s_rstin_fd_rst : std_logic;
signal s_counter_is_ten, s_counter_is_full : std_logic;
signal s_var_rst_counter_is_eight, s_var_rst_counter_is_two : std_logic;
signal s_var_rst_reinit_counter, s_var_rst_counter_is_full, s_var_rst_counter_full : std_logic;
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_var_rst_reinit_counter, s_var_rst_counter_is_full : std_logic;
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_rstin_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rsti_synch : std_logic_vector (2 downto 0);
type rstin_st_t is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
type after_a_var_rst_t is (after_a_var_rst_idle, after_a_var_rst_rston_ON,
after_a_var_rst_nFIP_ON_fd_ON_rston_ON,
after_a_var_rst_nFIP_OFF_fd_ON_rston_ON,
after_a_var_rst_nFIP_ON_fd_ON,
after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF);
signal after_a_var_rst_st, nx_after_a_var_rst_st : after_a_var_rst_t;
signal rstin_st, nx_rstin_st : rstin_st_t;
signal s_rsti_synch : std_logic_vector (2 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
s_transm_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
......@@ -244,23 +233,19 @@ begin
-- of 2 transm.
-- periods = 4
-- FD_TXCK periods
s_counter_full <= '1' when s_c = s_txck_four_periods else '0';
s_var_rst_counter_full <= '1' when s_var_rst_c = s_txck_four_periods else '0';
---------------------------------------------------------------------------------------------------
-- Power On Reset Synchronizers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronization of the de-assertion of the Power On reset, with the wb_clk.
--! The second flip-flop is used to remove metastabilities.
--! The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_i)
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
begin
if rstpon_i = '0' then
if rstpon_a_i = '0' then
s_wb_por_ff1 <= '1';
s_wb_por <= '1';
elsif rising_edge (wb_clk_i) then
......@@ -270,13 +255,13 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronization of the de-assertion of the Power On reset, with the uclk.
--! The second flip-flop is used to remove metastabilities.
--! The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_i)
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
begin
if rstpon_i = '0' then
if rstpon_a_i = '0' then
s_u_por_ff1 <= '1';
s_u_por <= '1';
elsif rising_edge (uclk_i) then
......@@ -308,138 +293,137 @@ begin
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! The FSM is following the "User Interface, General signal" RSTIN (after synchronization) and
--! checks whether it stays active for more than 4 uclk cycles; if so, it enables the nanoFIP
--! internal reset (s_intern_rst_from_RSTIN) and the FIELDRIVE reset (s_FD_rst_from_RSTIN). The
--! internal reset (s_rstin_nfip_rst) and the FIELDRIVE reset (s_rstin_fd_rst). The
--! nanoFIP internal reset stays active for 2 uclk cycles and the FIELDRIVE for 4 FD_TXCK cycles.
--! The same counter is used for the evaluation of the RSTIN (if it is > 4 uclk) and for the
--! generation of the two reset signals.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process RSTIN_FSM_Sync: Storage of the current state of the FSM.
--! The state machine can be reset by the Power On Reset and the variable reset.
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por = '1' or rst_nFIP_and_FD_p_i = '1' then
rstin_st <= idle;
rstin_st <= idle;
else
rstin_st <= nx_rstin_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_counter_is_four,
s_counter_is_ten, s_counter_is_full)
begin
case rstin_st is
when idle =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= rstin_eval;
case rstin_st is
else
when idle =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= rstin_eval;
else
nx_rstin_st <= idle;
end if;
when rstin_eval =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
when rstin_eval =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= idle;
else
if s_counter_is_four = '1' then -- counting the uclk cycles that
nx_rstin_st <= intern_rst_ON_fd_rst_ON;-- RSTIN is active
if s_counter_is_four = '1' then -- counting the uclk cycles that
nx_rstin_st <= nfip_on_fd_on; -- RSTIN is active
else
else
nx_rstin_st <= rstin_eval;
end if;
end if;
end if;
end if;
when intern_rst_ON_fd_rst_ON =>
when nfip_on_fd_on =>
if s_counter_is_ten = '1' then -- nanoFIP internal reset and
nx_rstin_st <= intern_rst_OFF_fd_rst_ON; -- FIELDRIVE reset active for
-- 2 uclk cycles
if s_counter_is_ten = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nfip_off_fd_on; -- FIELDRIVE reset active for
-- 2 uclk cycles
else
nx_rstin_st <= intern_rst_ON_fd_rst_ON;
nx_rstin_st <= nfip_on_fd_on;
end if;
when intern_rst_OFF_fd_rst_ON =>
when nfip_off_fd_on =>
-- nanoFIP internal reset deactivated
if s_counter_is_full = '1' then -- FIELDRIVE reset continues being active
nx_rstin_st <= idle; -- unitl 4 FD_TXCK cycles have passed
else
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
nx_rstin_st <= nfip_off_fd_on;
end if;
when others =>
when others =>
nx_rstin_st <= idle;
end case;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
--! the FSM. The process is handling the signals for the nanoFIP internal reset
--! (s_intern_rst_from_RSTIN) and the FIELDRIVE reset (s_FD_rst_from_RSTIN), as well as the inputs
--! of the RSTIN_free_counter.
--! the FSM. The process is handling the signals for the nanoFIP internal reset (s_rstin_nfip_rst)
--! and the FIELDRIVE reset (s_rstin_fd_rst), as well as the inputs of the RSTIN_free_counter.
RSTIN_FSM_Comb_Output_Signals: process (rstin_st)
begin
case rstin_st is
when idle =>
s_reinit_counter <= '1'; -- counter initialized
s_intern_rst_from_RSTIN <= '0';
s_FD_rst_from_RSTIN <= '0';
when rstin_eval =>
s_reinit_counter <= '0'; -- counting until 4
-- if RSTIN is active
s_intern_rst_from_RSTIN <= '0';
s_FD_rst_from_RSTIN <= '0';
case rstin_st is
when idle =>
s_reinit_counter <= '1'; -- counter initialized
s_rstin_nfip_rst <= '0';
s_rstin_fd_rst <= '0';
when intern_rst_ON_fd_rst_ON =>
s_reinit_counter <= '0'; -- free counter counting 2 uclk cycles
when rstin_eval =>
s_reinit_counter <= '0'; -- counting until 4
-- if RSTIN is active
s_rstin_nfip_rst <= '0';
s_rstin_fd_rst <= '0';
-------------------------------------
s_FD_rst_from_RSTIN <= '1'; -- FIELDRIVE active
s_intern_rst_from_RSTIN <= '1'; -- nFIP internal active
-------------------------------------
when nfip_on_fd_on =>
s_reinit_counter <= '0'; -- free counter counting 2 uclk cycles
when intern_rst_OFF_fd_rst_ON =>
s_reinit_counter <= '0'; -- free counter counting 4 FD_TXCK cycles
-------------------------------------
s_rstin_fd_rst <= '1'; -- FIELDRIVE active
s_rstin_nfip_rst <= '1'; -- nFIP internal active
-------------------------------------
s_intern_rst_from_RSTIN <= '0';
-------------------------------------
s_FD_rst_from_RSTIN <= '1'; -- FIELDRIVE active
-------------------------------------
when nfip_off_fd_on =>
s_reinit_counter <= '0'; -- free counter counting 4 FD_TXCK cycles
s_rstin_nfip_rst <= '0';
-------------------------------------
s_rstin_fd_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when others =>
s_reinit_counter <= '1'; -- no counting
s_reinit_counter <= '1'; -- no counting
s_rstin_fd_rst <= '0';
s_rstin_nfip_rst <= '0';
s_FD_rst_from_RSTIN <= '0';
s_intern_rst_from_RSTIN <= '0';
end case;
end case;
end process;
......@@ -449,19 +433,19 @@ begin
RSTIN_free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_is_full_o => open,
----------------------------------------
counter_o => s_c);
counter_o => s_rstin_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_counter_is_four <= '1' when s_c = to_unsigned(4, s_c'length) else '0';
s_counter_is_ten <= '1' when s_c = to_unsigned(10, s_c'length) else '0';
s_counter_is_full <= s_counter_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_counter_is_four <= '1' when s_rstin_c = to_unsigned(4, s_rstin_c'length) else '0';
s_counter_is_ten <= '1' when s_rstin_c = to_unsigned(10, s_rstin_c'length) else '0';
s_counter_is_full <= '1' when s_rstin_c = s_txck_four_periods else '0';
---------------------------------------------------------------------------------------------------
......@@ -473,191 +457,190 @@ RSTIN_free_counter: WF_incr_counter
--! If after the reception of a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
--! If after the reception of a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
--! asserts the nanoFIP internal reset (s_intern_rst_from_var_rst) for 2 uclk cycles and the
--! "nanoFIP FIELDRIVE" output (s_FD_rst_from_var_rst) for 4 FD_TXCK cycles.
--! asserts the nanoFIP internal reset (s_var_rst_nfip_rst) for 2 uclk cycles and the
--! "nanoFIP FIELDRIVE" output (s_var_rst_fd_rst) for 4 FD_TXCK cycles.
--! If after the reception of a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
--! are asserted, the FSM asserts the s_intern_rst_from_var_rst for 2 uclk cycles, the RSTON for 8
--! uclk cycles and the s_FD_rst_from_var_rst for 4 FD_TXCK cycles.
--! are asserted, the FSM asserts the s_var_rst_nfip_rst for 2 uclk cycles, the RSTON for 8
--! uclk cycles and the s_var_rst_fd_rst for 4 FD_TXCK cycles.
--! The same counter is used for all the countings!
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Resets_after_a_var_rst_synch: Storage of the current state of the FSM
--! The state machine can be reset by the Power On Reset and the nanoFIP internal reset from RSTIN.
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por = '1' or s_intern_rst_from_RSTIN = '1' then
after_a_var_rst_st <= after_a_var_rst_idle;
if s_u_por = '1' or s_rstin_nfip_rst = '1' then
var_rst_st <= var_rst_idle;
else
after_a_var_rst_st <= nx_after_a_var_rst_st;
var_rst_st <= nx_var_rst_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
--! state transitions of the FSM.
Resets_after_a_var_rst_Comb_State_Transitions: process (after_a_var_rst_st,var_i,rst_nFIP_and_FD_p_i,
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nFIP_and_FD_p_i,
assert_RSTON_p_i, s_var_rst_counter_is_two,
s_var_rst_counter_is_eight,
s_var_rst_counter_is_full)
begin
case after_a_var_rst_st is
when after_a_var_rst_idle =>
if (var_i = var_rst) and (assert_RSTON_p_i = '1')
and (rst_nFIP_and_FD_p_i = '1') then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON_rston_ON;
elsif (var_i = var_rst) and (assert_RSTON_p_i = '1') then
nx_after_a_var_rst_st <= after_a_var_rst_rston_ON;
elsif (var_i = var_rst) and (rst_nFIP_and_FD_p_i = '1') then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON;
else
nx_after_a_var_rst_st <= after_a_var_rst_idle;
case var_rst_st is
when var_rst_idle =>
if assert_RSTON_p_i = '1' and rst_nFIP_and_FD_p_i = '1' then
nx_var_rst_st <= var_rst_nfip_on_fd_on_rston_on;
elsif assert_RSTON_p_i = '1' then
nx_var_rst_st <= var_rst_rston_on;
elsif rst_nFIP_and_FD_p_i = '1' then
nx_var_rst_st <= var_rst_nfip_on_fd_on;
else
nx_var_rst_st <= var_rst_idle;
end if;
when after_a_var_rst_rston_ON => -- for 8 uclk cycles
if s_var_rst_counter_is_eight = '1' then
nx_after_a_var_rst_st <= after_a_var_rst_idle;
when var_rst_rston_on => -- for 8 uclk cycles
if s_var_rst_counter_is_eight = '1' then
nx_var_rst_st <= var_rst_idle;
else
nx_after_a_var_rst_st <= after_a_var_rst_rston_ON;
end if;
nx_var_rst_st <= var_rst_rston_on;
end if;
when var_rst_nfip_on_fd_on_rston_on => -- for 2 uclk cycles
if s_var_rst_counter_is_two = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_on;
when after_a_var_rst_nFIP_ON_fd_ON_rston_ON => -- for 2 uclk cycles
if s_var_rst_counter_is_two = '1' then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_ON;
else
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON_rston_ON;
nx_var_rst_st <= var_rst_nfip_on_fd_on_rston_on;
end if;
when after_a_var_rst_nFIP_OFF_fd_ON_rston_ON => -- for 6 uclk cycles
if s_var_rst_counter_is_eight = '1' then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
when var_rst_nfip_off_fd_on_rston_on => -- for 6 uclk cycles
if s_var_rst_counter_is_eight = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
else
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_ON;
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_on;
end if;
when after_a_var_rst_nFIP_ON_fd_ON => -- for 2 uclk cycles
if s_var_rst_counter_is_two = '1' then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
when var_rst_nfip_on_fd_on => -- for 2 uclk cycles
if s_var_rst_counter_is_two = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
else
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON;
nx_var_rst_st <= var_rst_nfip_on_fd_on;
end if;
when after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF => -- until the filling-up of the counter
if s_var_rst_counter_is_full = '1' then
nx_after_a_var_rst_st <= after_a_var_rst_idle;
when var_rst_nfip_off_fd_on_rston_off => -- until the filling-up of the counter
if s_var_rst_counter_is_full = '1' then
nx_var_rst_st <= var_rst_idle;
else
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
end if;
when others =>
nx_after_a_var_rst_st <= after_a_var_rst_idle;
end case;
when others =>
nx_var_rst_st <= var_rst_idle;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
--! the FSM. The process is managing the signals for the nanoFIP internal reset and the FIELDRIVE
--! reset, as well as the arguments of the counter.
rst_var_FSM_Comb_Output_Signals: process (after_a_var_rst_st)
rst_var_FSM_Comb_Output_Signals: process (var_rst_st)
begin
case after_a_var_rst_st is
when after_a_var_rst_idle =>
s_var_rst_reinit_counter <= '1'; -- counter initialized
s_rston <= '0';
s_intern_rst_from_var_rst <= '0';
s_FD_rst_from_var_rst <= '0';
case var_rst_st is
when after_a_var_rst_rston_ON =>
s_var_rst_reinit_counter <= '0'; -- counting 8 uclk cycles
when var_rst_idle =>
s_var_rst_reinit_counter <= '1'; -- counter initialized
s_rston <= '0';
s_var_rst_nfip_rst <= '0';
s_var_rst_fd_rst <= '0';
when var_rst_rston_on =>
s_var_rst_reinit_counter <= '0'; -- counting 8 uclk cycles
-------------------------------------
s_rston <= '1'; -- RSTON active
s_rston <= '1'; -- RSTON active
-------------------------------------
s_intern_rst_from_var_rst <= '0';
s_FD_rst_from_var_rst <= '0';
s_var_rst_nfip_rst <= '0';
s_var_rst_fd_rst <= '0';
when after_a_var_rst_nFIP_ON_fd_ON_rston_ON =>
s_var_rst_reinit_counter <= '0'; -- counting 2 uclk cycles
when var_rst_nfip_on_fd_on_rston_on =>
s_var_rst_reinit_counter <= '0'; -- counting 2 uclk cycles
-------------------------------------
s_rston <= '1'; -- RSTON active
s_intern_rst_from_var_rst <= '1'; -- nFIP internal active
s_FD_rst_from_var_rst <= '1'; -- FIELDRIVE active
s_rston <= '1'; -- RSTON active
s_var_rst_nfip_rst <= '1'; -- nFIP internal active
s_var_rst_fd_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when after_a_var_rst_nFIP_OFF_fd_ON_rston_ON =>
s_var_rst_reinit_counter <= '0'; -- counting 6 uclk cycles
when var_rst_nfip_off_fd_on_rston_on =>
s_var_rst_reinit_counter <= '0'; -- counting 6 uclk cycles
s_intern_rst_from_var_rst <= '0';
s_var_rst_nfip_rst <= '0';
-------------------------------------
s_rston <= '1'; -- RSTON active
s_FD_rst_from_var_rst <= '1'; -- FIELDRIVE active
s_rston <= '1'; -- RSTON active
s_var_rst_fd_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when after_a_var_rst_nFIP_ON_fd_ON =>
s_var_rst_reinit_counter <= '0'; -- counting 2 uclk cycles
when var_rst_nfip_on_fd_on =>
s_var_rst_reinit_counter <= '0'; -- counting 2 uclk cycles
s_rston <= '0';
-------------------------------------
s_intern_rst_from_var_rst <= '1'; -- nFIP internal active
s_FD_rst_from_var_rst <= '1'; -- FIELDRIVE active
-------------------------------------
s_rston <= '0';
-------------------------------------
s_var_rst_nfip_rst <= '1'; -- nFIP internal active
s_var_rst_fd_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF =>
s_var_rst_reinit_counter <= '0'; -- counting 4 FD_TXCK cycles
s_rston <= '0';
s_intern_rst_from_var_rst <= '0';
-------------------------------------
s_FD_rst_from_var_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when var_rst_nfip_off_fd_on_rston_off =>
s_var_rst_reinit_counter <= '0'; -- counting 4 FD_TXCK cycles
s_rston <= '0';
s_var_rst_nfip_rst <= '0';
-------------------------------------
s_var_rst_fd_rst <= '1'; -- FIELDRIVE active
-------------------------------------
when others =>
s_var_rst_reinit_counter <= '1'; -- no counting
s_var_rst_reinit_counter <= '1'; -- no counting
s_rston <= '0';
s_var_rst_nfip_rst <= '0';
s_var_rst_fd_rst <= '0';
s_rston <= '0';
s_intern_rst_from_var_rst <= '0';
s_FD_rst_from_var_rst <= '0';
end case;
end case;
end process;
......@@ -670,7 +653,7 @@ RSTIN_free_counter: WF_incr_counter
free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
uclk_i => uclk_i,
reinit_counter_i => s_var_rst_reinit_counter,
incr_counter_i => '1',
counter_is_full_o => open,
......@@ -678,10 +661,10 @@ free_counter: WF_incr_counter
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
s_var_rst_counter_is_two <= '1' when s_var_rst_c= to_unsigned(10, s_var_rst_c'length) else '0';
s_var_rst_counter_is_full <= s_var_rst_counter_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
s_var_rst_counter_is_two <= '1' when s_var_rst_c= to_unsigned(10, s_var_rst_c'length) else '0';
s_var_rst_counter_is_full <= '1' when s_var_rst_c= s_txck_four_periods else '0';
......@@ -690,15 +673,15 @@ free_counter: WF_incr_counter
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por;
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_u_por;
nFIP_rst_o <= s_rstin_nfip_rst or s_var_rst_nfip_rst or s_u_por;
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por, s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst)
RSTON_Buffering: process (uclk_i, s_u_por, s_rstin_nfip_rst, s_var_rst_nfip_rst)
begin
if s_intern_rst_from_RSTIN = '1' or s_intern_rst_from_var_rst = '1' or s_u_por = '1' then
rston_o <= '1';
if s_rstin_nfip_rst = '1' or s_var_rst_nfip_rst = '1' or s_u_por = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= not s_rston;
rston_o <= not s_rston;
end if;
end process;
......@@ -706,7 +689,7 @@ free_counter: WF_incr_counter
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_u_por);
fd_rstn_o <= not (s_rstin_fd_rst or s_var_rst_fd_rst or s_u_por);
end if;
end process;
......
wf_rx_deglitcher.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details
--! @details
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -49,7 +49,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
......@@ -73,19 +73,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_rx_deglitcher is
port(
-- INPUTS
-- nanoFIP User Interface general signal
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; --! receiver data
fd_rxd_a_i : in std_logic; --! receiver data
-- OUTPUTS
-- OUTPUTS
-- Signals to the WF_rx_deserializer unit
fd_rxd_filtered_o : out std_logic; --! filtered output signal
fd_rxd_filtered_edge_p_o : out std_logic; --! indicates an edge on the filtered signal
......@@ -125,7 +125,7 @@ begin
else
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if;
end if;
end if;
end process;
......@@ -158,7 +158,7 @@ begin
if s_deglitch_c /= c_DEGLITCH_THRESHOLD then
s_deglitch_c <= s_deglitch_c + 1; -- counter updated
else
s_rxd_filtered <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD
......
wf_rx_deserializer.vhd
View file @ 297713da
......@@ -45,7 +45,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: _|-, bit 1: -|_).
--!
--! o a transition : for the moment in between two adjacent bits,
--! o a transition : for the moment in between two adjacent bits,
--! that may or may not result in an edge (eg. a 0 followed by a 0 will give an edge
--! _|-|_|-, but a 0 followed by a 1 will not _|--|_ ).
--!
......@@ -53,14 +53,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! should be sampled, before and after a significant edge.
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition.
--! before the transition.
--!
--! Example:
--! bits : 0 1
--! bits : 0 1
--! manch. encoded : _|- -|_
--! significant edge : ^ ^
--! transition : ^
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--!
--!
......@@ -82,32 +82,32 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.05
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_osc \n
--! WF_rx_deglitcher \n
--! WF_engine_control \n
--
--
--
--
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 09/2009 v0.01 PAS First version \n
--! -> 10/2010 v0.02 EG state switch_to_deglitched added;
--! output signal rx_osc_rst_o added; signals renamed;
--! state machine rewritten (moore style);
--! state machine rewritten (moore style);
--! units WF_rx_manch_code_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--! -> 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! like this we confirm that the CRC_ok_p arrived just before the FES,
--! and any 2 bytes that could by chanche be seen as CRC, are neglected.
--! and any 2 bytes that could by chanche be seen as CRC, are neglected.
--! FSM data_field_byte state: redundant code removed:
--! "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
--! code(more!)cleaned-up
......@@ -115,11 +115,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! bytes with size different than 8 have preceeded.
--! crc_or_manch_wrong_p_o replaced the crc_wrong_p_o.
--! -> 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! ->
--
---------------------------------------------------------------------------------------------------
......@@ -132,10 +132,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_rx_deserializer is
port (
-- INPUTS
-- nanoFIP User Interface general signal
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......@@ -145,30 +145,30 @@ entity WF_rx_deserializer is
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- Signals from the WF_rx_deglitcher
fd_rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on the deglitched fd_rxd
fd_rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on the deglitched fd_rxd
fd_rxd_r_edge_p_i : in std_logic; --! indicates a rising edge on the deglitched fd_rxd
fd_rxd_i : in std_logic; --! deglitched fd_rxd
-- Signals from the WF_rx_osc unit
sample_manch_bit_p_i : in std_logic; --! pulse indicating the sampling of a manch. bit
sample_manch_bit_p_i : in std_logic; --! pulse indicating the sampling of a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating the sampling of a bit
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- OUTPUTS
-- Signals to the WF_consumption and the WF_engine_control units
-- Signals to the WF_consumption and the WF_engine_control units
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a new retrieved data byte
fss_crc_fes_manch_ok_p_o: out std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
-- Signal to the WF_production and the WF_engine_control units
-- Signal to the WF_production and the WF_engine_control units
crc_or_manch_wrong_p_o : out std_logic; --! indication of a wrong CRC or manch. encoding on a
--! ID_DAT or RP_DAT; pulse after the FES detection
-- Signal to the WF_engine_control unit
-- Signal to the WF_engine_control unit
fss_received_p_o : out std_logic; --! pulse after the reception of a correct FSS (ID/RP)
-- Signal to the WF_rx_osc unit
......@@ -182,7 +182,7 @@ end entity WF_rx_deserializer;
--! architecture declaration
--=================================================================================================
architecture rtl of WF_rx_deserializer is
-- states of the receiver's state machine
type rx_st_t is (idle, pre_field_first_f_edge, pre_field_r_edge, pre_field_f_edge,
fsd_field, ctrl_data_fcs_fes_fields);
......@@ -193,7 +193,7 @@ architecture rtl of WF_rx_deserializer is
signal s_fsd_last_bit, s_fes_wrong_bit, s_fes_detected_p : std_logic;
signal s_byte_ready_p, s_byte_ready_p_d1, s_write_bit_to_byte_p : std_logic;
signal s_manch_r_edge_p, s_manch_f_edge_p, s_bit_r_edge_p, s_edge_out_manch_window_p : std_logic;
signal s_manch_bit_index_load, s_decr_manch_bit_index_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_bit_index_load, s_decr_manch_bit_index_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_not_ok, s_manch_code_viol_p,s_CRC_ok_p,s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned (3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
......@@ -202,7 +202,7 @@ architecture rtl of WF_rx_deserializer is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -213,7 +213,7 @@ architecture rtl of WF_rx_deserializer is
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Deserializer_FSM_Sync: storage of the current state of the FSM
Deserializer_FSM_Sync: process (uclk_i)
......@@ -226,12 +226,12 @@ architecture rtl of WF_rx_deserializer is
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Deserializer_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_out_manch_window_p,
rx_rst_p_i, fd_rxd_f_edge_p_i, s_manch_r_edge_p,
s_fsd_wrong_bit, s_manch_f_edge_p, rx_st,
......@@ -239,16 +239,16 @@ architecture rtl of WF_rx_deserializer is
begin
-- During the PRE, the WF_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the deglitched FD_RXD is taken into account. At this phase, the unit uses
-- edge detected in the deglitched FD_RXD is taken into account. At this phase, the unit uses
-- the WF_rx_osc signals adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to idle and the WF_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the WF_rx_osc signals sample_manch_bit_p_i and sample_bit_p_i.
case rx_st is
case rx_st is
when idle => -- in idle state until falling
when idle => -- in idle state until falling
if fd_rxd_f_edge_p_i = '1' then -- edge detection
nx_rx_st <= pre_field_first_f_edge;
......@@ -257,67 +257,67 @@ architecture rtl of WF_rx_deserializer is
else
nx_rx_st <= idle;
end if;
end if;
when pre_field_first_f_edge=>
if s_manch_r_edge_p = '1' then -- arrival of a "manch."
if s_manch_r_edge_p = '1' then -- arrival of a "manch."
nx_rx_st <= pre_field_r_edge; -- rising edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
else
nx_rx_st <= pre_field_first_f_edge;
end if;
end if;
when pre_field_r_edge =>
if s_manch_f_edge_p = '1' then -- arrival of a manch. falling edge
when pre_field_r_edge =>
if s_manch_f_edge_p = '1' then -- arrival of a manch. falling edge
nx_rx_st <= pre_field_f_edge; -- note: several loops between
-- a rising and a falling edge are
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_r_edge;
end if;
when pre_field_f_edge =>
when pre_field_f_edge =>
if s_manch_r_edge_p = '1' then -- arrival of a manch. rising edge
nx_rx_st <= pre_field_r_edge;
nx_rx_st <= pre_field_r_edge;
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= fsd_field; -- adjacent bits, signaling the
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= fsd_field; -- adjacent bits, signaling the
-- beginning of the 1st V+ violation
-- of the FSD
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_f_edge;
end if;
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- filtered signal and it is comparing it to the nominal bit of the FSD (through the signal
-- s_fsd_wrong_bit). If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the ctrl_data_fcs_fes_fields
when fsd_field =>
if s_fsd_last_bit = '1' then -- reception of the last(15th)
if s_fsd_last_bit = '1' then -- reception of the last(15th)
nx_rx_st <= ctrl_data_fcs_fes_fields;-- FSD bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
......@@ -325,18 +325,18 @@ architecture rtl of WF_rx_deserializer is
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= fsd_field;
nx_rx_st <= fsd_field;
end if;
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 134 bytes (FSS+Ctrl+PDU_TYPE+LGTH+125 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number exceeds the expected one, it activates the signal rx_rst_p_i.
-- Therefore, the Receiver_FSM stays in the ctrl_data_fcs_fes_fields state until the arrival
-- of a correct FES, or until the arrival of a reset signal from the WF_engine_control.
-- of a correct FES, or until the arrival of a reset signal from the WF_engine_control.
when ctrl_data_fcs_fes_fields =>
if s_fes_detected_p = '1' then
......@@ -350,25 +350,25 @@ architecture rtl of WF_rx_deserializer is
else
nx_rx_st <= ctrl_data_fcs_fes_fields;
end if;
end if;
when others =>
when others =>
nx_rx_st <= idle;
end case;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Deserializer_FSM_Comb_Output_Signals: definition of the output
--! signals of the FSM
Deserializer_FSM_Comb_Output_Signals: process (rx_st)
begin
case rx_st is
case rx_st is
when idle =>
------------------------------------
s_idle <= '1';
......@@ -377,7 +377,7 @@ architecture rtl of WF_rx_deserializer is
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when pre_field_first_f_edge | pre_field_r_edge | pre_field_f_edge =>
s_idle <= '0';
......@@ -397,7 +397,7 @@ architecture rtl of WF_rx_deserializer is
------------------------------------
s_receiving_bytes <= '0';
when ctrl_data_fcs_fes_fields =>
s_idle <= '0';
......@@ -407,15 +407,15 @@ architecture rtl of WF_rx_deserializer is
s_receiving_bytes <= '1';
------------------------------------
when others =>
when others =>
s_idle <= '0';
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
end case;
end case;
end process;
......@@ -433,21 +433,21 @@ architecture rtl of WF_rx_deserializer is
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte_ready_p_d1 <='0';
s_byte_ready_p_d1 <='0';
s_byte <= (others => '0');
else
s_byte_ready_p_d1 <= s_byte_ready_p;
s_byte_ready_p_d1 <= s_byte_ready_p;
if s_write_bit_to_byte_p = '1' then
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte_p <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
and (not s_fes_detected_p);
......@@ -460,12 +460,12 @@ architecture rtl of WF_rx_deserializer is
--!@brief Instantiation of a counter that manages the position of an incoming deglitched bit
--! inside a manch. encoded byte (16 bits).
Incoming_Bits_Index: WF_decr_counter
generic map (g_counter_lgth => 4)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load,
counter_decr_p_i => s_decr_manch_bit_index_p,
......@@ -475,20 +475,20 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
-- FES aux signals concurrent assignments :
s_fes_bit <= s_receiving_bytes and c_FES (to_integer(s_manch_bit_index));
s_fes_wrong_bit <= (s_fes_bit xor fd_rxd_i) and sample_manch_bit_p_i;
s_fes_wrong_bit <= (s_fes_bit xor fd_rxd_i) and sample_manch_bit_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process that according to the state of the FSM sets values to the
--! Incoming_Bits_Index inputs.
......@@ -497,12 +497,12 @@ architecture rtl of WF_rx_deserializer is
begin
if s_idle ='1' then -- counter re-initialization after a reception
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '1';
s_decr_manch_bit_index_p <= '0';
elsif s_receiving_pre = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(c_FSD'left-2,s_manch_bit_index_top'length);
s_manch_bit_index_top <= to_unsigned(c_FSD'left-2,s_manch_bit_index_top'length);
-- FSD'left-2: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= '0';
......@@ -512,27 +512,27 @@ architecture rtl of WF_rx_deserializer is
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= sample_manch_bit_p_i;
elsif s_receiving_bytes = '1' then -- counting manch. encoded data bits
s_manch_bit_index_top <= to_unsigned (15, s_manch_bit_index_top'length);
elsif s_receiving_bytes = '1' then -- counting manch. encoded data bits
s_manch_bit_index_top <= to_unsigned (15, s_manch_bit_index_top'length);
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= sample_manch_bit_p_i;
else
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
--! manch. encoded bits received and the s_fes_detected_p indicates whether they match the FES.
--! manch. encoded bits received and the s_fes_detected_p indicates whether they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_receiving_bytes = '0' then
if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
......@@ -543,9 +543,9 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- 1 uclk-wide pulse after the FES detection
s_fes_detected_p <= '1' when (s_arriving_fes = c_FES) and (s_byte_ready_p_d1 = '1') else '0';
s_fes_detected_p <= '1' when (s_arriving_fes = c_FES) and (s_byte_ready_p_d1 = '1') else '0';
......@@ -555,7 +555,7 @@ architecture rtl of WF_rx_deserializer is
--!@brief Instantiation of the CRC calculator unit that verifies the received FCS field.
CRC_Verification : WF_crc
CRC_Verification : WF_crc
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -568,7 +568,7 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the WF_rx_manch_code_check unit that checks for manch. code violations.
Manch_Encoding_Verification: WF_rx_manch_code_check
......@@ -583,10 +583,10 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that handles the s_manch_code_viol_p signal: If at any point after
--! the FSS and before the FES a code violation appears, the signal s_manch_not_ok stays
--! asserted until the end of the corresponding frame.
--! asserted until the end of the corresponding frame.
Code_viol: process (uclk_i)
begin
......@@ -595,16 +595,16 @@ architecture rtl of WF_rx_deserializer is
s_manch_not_ok <= '0';
else
if s_manch_code_viol_p ='1' and s_fes_wrong_bit ='1' then
s_manch_not_ok <= '1'; -- if a code violation appears
-- that doesn't belong to the FES
end if;
if s_manch_code_viol_p ='1' and s_fes_wrong_bit ='1' then
s_manch_not_ok <= '1'; -- if a code violation appears
-- that doesn't belong to the FES
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that checks the position of the CRC bytes in the frame: the 1 uclk-
--! wide crc_ok_p coming from the CRC calculator is delayed for 1 complete byte. The matching of
--! this delayed pulse with the end of frame pulse (s_fes_detected_p), would confirm that the two
......@@ -618,20 +618,20 @@ architecture rtl of WF_rx_deserializer is
s_CRC_ok_p_found <= '0';
else
if s_CRC_ok_p = '1' then
if s_CRC_ok_p = '1' then
s_CRC_ok_p_found <= '1';
end if;
if s_byte_ready_p = '1' and s_CRC_ok_p_found = '1' then -- arrival of the next byte
s_CRC_ok_p_d <= '1'; -- (FES normally)
s_CRC_ok_p_found <= '0';
else
else
s_CRC_ok_p_d <= '0';
end if;
end if;
end if;
end if;
end process;
......@@ -671,10 +671,10 @@ architecture rtl of WF_rx_deserializer is
s_edge_out_manch_window_p <= (not signif_edge_window_i)and(fd_rxd_r_edge_p_i or fd_rxd_f_edge_p_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals concurrent assignments :
byte_o <= s_byte;
byte_o <= s_byte;
byte_ready_p_o <= s_byte_ready_p_d1;
rx_osc_rst_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
......
wf_rx_osc.vhd
View file @ 297713da
......@@ -67,13 +67,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection;code cleanedup+commented
--! rst_rx_osc signal clearified
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
--! -> 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo -->
--! @todo -->
--
---------------------------------------------------------------------------------------------------
......@@ -88,22 +88,22 @@ entity WF_rx_osc is
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_deglitcher unit
-- Signal from the WF_deglitcher unit
fd_rxd_edge_p_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from WF_rx_deserializer unit
-- Signal from WF_rx_deserializer unit
rx_osc_rst_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- OUTPUTS
-- Signals to the WF_rx_deserializer
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o on a significant edge
--! o on a significant edge
--! o between adjacent bits
--! ____|-|___|-|___|-|___
......@@ -112,7 +112,7 @@ entity WF_rx_osc is
--! __________|-|_________
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic --! time window where a transition between adjacent
--! bits is expected
);
......@@ -139,8 +139,8 @@ architecture rtl of WF_rx_osc is
--=================================================================================================
begin
-- # uclock ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
-- # uclock ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
s_half_period <= s_period srl 1; -- 1/2 s_period
......@@ -168,10 +168,10 @@ begin
incr_counter_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if nfip_rst_i is active or
-- if the rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
......@@ -185,21 +185,21 @@ begin
--! nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- In detail, the process is looking for moments :
-- o of significant edges
-- o of significant edges
-- o between boundary bits
-- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- is inverted right after the end of the signif_edge_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clks: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
......@@ -215,10 +215,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
......@@ -226,7 +226,7 @@ begin
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then
s_manch_clk <= not s_manch_clk;
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
......@@ -235,7 +235,7 @@ begin
-- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk
......@@ -246,38 +246,38 @@ begin
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
s_bit_clk <= not s_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
s_manch_clk_d1 <= s_manch_clk;
-- s_manch_clk: ____|-----|_____|-----|____
-- s_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_bit_clk_d1 <= s_bit_clk;
s_bit_clk_d1 <= s_bit_clk;
-- s_bit_clk: ____|-----------|___________
-- s_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
end if;
end if;
end process;
end process;
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignments: creation of the windows where
--! "significant edges" and "adjacent bits transitions" are expected on the input signal.
--! o s_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! o s_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the completion of a period, where significant edges are expected.
--! o s_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected.
--! o s_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_jitter) or
(s_period_c > s_period-1 - s_jitter-1))
......@@ -293,7 +293,7 @@ begin
-- Output signals concurrent assignments
rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after
-- o a significant edge
-- o a significant edge
-- o a new bit
-- ___|-|___|-|___|-|___
......
wf_status_bytes_gen.vhd
View file @ 297713da
......@@ -30,7 +30,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief Generation of the nanoFIP status and MPS status bytes.
--! The unit is also responsible for outputting the "nanoFIP User Interface,
--! The unit is also responsible for outputting the "nanoFIP User Interface,
--! NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to nanoFIP
--! status bits 2 to 5.
--!
......@@ -45,7 +45,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC is used.
--!
--! The MPS status byte and the bits 0 to 5 of the nanoFIP status byte are reset after
--! having been sent.
--! having been sent.
--!
--!
--! Reminder:
......@@ -70,22 +70,22 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |______________________|__________|____________________________________|
--!
--! ---------------------------------------------------------------------------
--! __________________ ______________ ______________
--! __________________ ______________ ______________
--! | MPS STATUS BIT | NAME | CONTENTS |
--! |__________________|______________|______________|
--! | 0 | refreshment | 1/0 |
--! |__________________|______________|______________|
--! | 1 | | 0 |
--! |__________________|______________|______________|
--! | 2 | significance | 1/0 |
--! |__________________|______________|______________|
--! |__________________|______________|______________|
--! | 0 | refreshment | 1/0 |
--! |__________________|______________|______________|
--! | 1 | | 0 |
--! |__________________|______________|______________|
--! | 2 | significance | 1/0 |
--! |__________________|______________|______________|
--! | 3 | | 0 |
--! |__________________|_____________ |______________|
--! | 4-7 | | 000 |
--! |__________________|_____________ |______________|
--!
--! |__________________|_____________ |______________|
--! | 4-7 | | 000 |
--! |__________________|_____________ |______________|
--!
--! The refreshment and significance are set to 1 if the user has updated
--! the produced variable since the last transmission of the variable
--! the produced variable since the last transmission of the variable
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -98,7 +98,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! @details\n
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
......@@ -124,7 +124,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! @todo
--
---------------------------------------------------------------------------------------------------
......@@ -136,7 +136,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_status_bytes_gen is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! stand-alone mode
......@@ -149,11 +149,11 @@ port (
fd_wdgn_a_i : in std_logic; --! watchdog on transmitter
-- nanoFIP User Interface, NON-WISHBONE
var1_acc_a_i : in std_logic; --! variable 1 access
var2_acc_a_i : in std_logic; --! variable 2 access
var1_acc_a_i : in std_logic; --! variable 1 access
var2_acc_a_i : in std_logic; --! variable 2 access
var3_acc_a_i : in std_logic; --! variable 3 access
-- Signals from the WF_consumption unit
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; --! wrong CRC bytes received
nfip_status_r_tler_p_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
var1_rdy_i : in std_logic; --! variable 1 ready
......@@ -168,7 +168,7 @@ port (
var3_rdy_i : in std_logic; --! variable 3 ready
-- OUTPUTS
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
......@@ -178,7 +178,7 @@ port (
-- Signal to the WF_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); --! MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0) --! nanoFIP status byte
);
);
end entity WF_status_bytes_gen;
--=================================================================================================
......@@ -188,7 +188,7 @@ architecture rtl of WF_status_bytes_gen is
signal s_incr_var1_rdy_counter, s_reinit_var1_rdy_counter, s_var1_rdy_extended : std_logic;
signal s_incr_var2_rdy_counter, s_reinit_var2_rdy_counter, s_var2_rdy_extended : std_logic;
signal s_incr_var3_rdy_counter, s_reinit_var3_rdy_counter, s_var3_rdy_extended : std_logic;
signal s_incr_var3_rdy_counter, s_reinit_var3_rdy_counter, s_var3_rdy_extended : std_logic;
signal s_refreshment : std_logic;
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
......@@ -213,21 +213,21 @@ begin
else
s_fd_wdg_synch <= s_fd_wdg_synch (1 downto 0) & not fd_wdgn_a_i;
s_fd_txer_synch <= s_fd_txer_synch (1 downto 0) & fd_txer_a_i;
end if;
s_fd_txer_synch <= s_fd_txer_synch (1 downto 0) & fd_txer_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronizer: process (uclk_i)
VAR_ACC_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_acc_synch <= (others => '0');
s_var2_acc_synch <= (others => '0');
s_var3_acc_synch <= (others => '0');
else
s_var1_acc_synch <= s_var1_acc_synch(1 downto 0) & var1_acc_a_i;
s_var2_acc_synch <= s_var2_acc_synch(1 downto 0) & var2_acc_a_i;
......@@ -246,16 +246,16 @@ begin
--! the MPS status byte). The bit is set to 1 if the user has updated the produced variable since
--! its last transmission. The process is checking if the signal VAR3_ACC has been asserted since
--! the last production of a variable.
Refreshment_bit_Creation: process (uclk_i)
Refreshment_bit_Creation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if nfip_rst_i = '1' then
s_refreshment <= '0';
else
if rst_status_bytes_p_i = '1' then -- bit reinitialized after a var production
s_refreshment <= '0';
s_refreshment <= '0';
elsif (var3_acc_a_i = '1') then -- indication that the memory has been accessed
s_refreshment <= '1';
......@@ -269,20 +269,20 @@ end process;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process MPS_byte_Creation: Creation of the MPS byte
--! (nanoFIP functional specification, Table 2)
MPS_byte_Creation: process (slone_i, s_refreshment)
begin
if slone_i='1' then
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_status_byte_o (c_REFRESHMENT_INDEX) <= '1';
else
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if;
......@@ -295,23 +295,23 @@ end process;
--! @brief Synchronous process Status_byte_Formation: Formation of the nanoFIP status byte
--! (nanoFIP functional specification, Table 8)
nFIP_status_byte_generation: process (uclk_i)
nFIP_status_byte_generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_nFIP_status_byte <= (others => '0');
if nfip_rst_i = '1' then
s_nFIP_status_byte <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialisation after the transmission of a produced variable
-- reinitialization after the transmission of a produced variable
if rst_status_bytes_p_i = '1' then -- bits 0 to 5 reinitialised
s_nFIP_status_byte(5 downto 0) <= (others => '0'); -- after having been delivered
-- bits 6 and 7 are only reset
-- when nanoFIP is reset
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_cacer
if ((s_var1_rdy_extended = '0' and s_var1_acc_synch(2) = '1') or
......@@ -320,22 +320,22 @@ end process;
-- byte was delivered,
s_nFIP_status_byte(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cons.
-- var. when it was not ready
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_pacer
if (s_var3_rdy_extended = '0' and s_var3_acc_synch(2) = '1') then
-- since the last time the status
if (s_var3_rdy_extended = '0' and s_var3_acc_synch(2) = '1') then
-- since the last time the status
s_nFIP_status_byte(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
-- the user logic accessed a prod.
-- var. when it was not ready
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
......@@ -349,18 +349,18 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
if (nfip_status_r_tler_p_i = '1') then
if (nfip_status_r_tler_p_i = '1') then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
if (nfip_status_r_fcser_p_i = '1') then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
end if;
......@@ -371,7 +371,7 @@ end process;
--!@brief Instantiation of 3 WF_incr_counters used for the internal extension of each one of the
--! signals VAR1_RDY, VAR2_RDY, VAR3_RDY for 15 uclk cycles.
--! Enabled VAR_ACC during this period will not trigger an error.
Extend_VAR1_RDY: WF_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map (g_counter_lgth => 4) -- s_var1_rdy_extended : __|---...------------------|____
port map (
......@@ -380,8 +380,8 @@ end process;
incr_counter_i => s_incr_var1_rdy_counter,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var1_rdy_c);
------------------------------------------
counter_o => s_var1_rdy_c);
------------------------------------------
s_reinit_var1_rdy_counter <= var1_rdy_i or nfip_rst_i;
s_incr_var1_rdy_counter <= '1' when s_var1_rdy_c < "1111" else '0';
......@@ -424,9 +424,9 @@ end process;
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
nFIP_status_byte_o <= s_nFIP_status_byte;
u_cacer_o <= s_nFIP_status_byte(c_U_CACER_INDEX);
u_cacer_o <= s_nFIP_status_byte(c_U_CACER_INDEX);
u_pacer_o <= s_nFIP_status_byte(c_U_PACER_INDEX);
r_tler_o <= s_nFIP_status_byte(c_R_TLER_INDEX);
r_fcser_o <= s_nFIP_status_byte(c_R_FCSER_INDEX);
......
wf_tx_osc.vhd
View file @ 297713da
......@@ -29,14 +29,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock)
--! and the nanoFIP internal signal tx_clk_p_buff:
--!
--!
--! uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|
--! FD_TXCK : _____|--------...--------|________...________|--------...--------|__
--! tx_clk_p_buff(3) : 0 0 0 1 0 0 0 1
--! tx_clk_p_buff(2) : 0 0 1 0 0 0 1 0
--! tx_clk_p_buff(1) : 0 1 0 0 0 1 0 0
--! tx_clk_p_buff(0) : 1 0 0 0 1 0 0 0
--!
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -63,13 +63,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! -> 12/2010 v0.03 EG code cleaned-up
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo -->
--! @todo -->
--
---------------------------------------------------------------------------------------------------
......@@ -84,22 +84,22 @@ entity WF_tx_osc is
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
tx_osc_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
-- OUTPUTS
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Signal to the WF_tx_serializer unit
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
);
end entity WF_tx_osc;
......@@ -116,12 +116,12 @@ architecture rtl of WF_tx_osc is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p, s_counter_is_full, s_reinit_counter : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclock ticks for a
-- transmission period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
......@@ -140,10 +140,10 @@ begin
incr_counter_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
......@@ -155,7 +155,7 @@ begin
--!@brief Clocks Constraction: Concurrent signals assignments and a synchronous process that use
--! the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_clk_p_buff_o.
-- Creation of the clock for the transmitter with period: 1/2 transmission period
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or
((s_period_c > (2*s_one_forth_period)-1) and
(s_period_c < 3*s_one_forth_period)))
......@@ -166,21 +166,21 @@ begin
-- Creation of a pulse starting 1 uclk period before tx_clk_o
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
-- not s_tx_clk_d1 : ----|_____|-----|_____|---
-- s_tx_clk_p : __|-|___|-|___|-|___|-|___
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_Signals_Construction: process (uclk_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
else
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left-1 downto 0) & s_tx_clk_p;
......@@ -195,7 +195,7 @@ begin
--!@brief Output signals assignments
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
......
wf_tx_serializer.vhd
View file @ 297713da
......@@ -52,7 +52,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--!
--! |------------- Bytes from the WF_production -------------|
--!
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -64,7 +64,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @version v0.04
--
--! @details\n
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
......@@ -82,16 +82,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> v0.02 2009 PAS Entity Ports added, start of architecture content
--! -> v0.03 07/2010 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! renamed from tx to tx_serializer;
--! stop_transmission state added for the synch of txena
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! renamed from tx to tx_serializer;
--! stop_transmission state added for the synch of txena
--! -> v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the
--! clock buffer available(tx_start_p_i may arrive at any time)
--! clock buffer available(tx_start_p_i may arrive at any time)
--
---------------------------------------------------------------------------------------------------
--
--! @todo -> bit simpler?
--
--
---------------------------------------------------------------------------------------------------
......@@ -100,24 +100,24 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_tx_serializer is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_production
byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control unit
tx_start_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
-- Signal from the WF_tx_osc
-- Signal from the WF_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--! clk for the transmission synchronization
--! clk for the transmission synchronization
-- OUTPUTS
......@@ -149,7 +149,7 @@ architecture rtl of WF_tx_serializer is
signal s_session_timedout : std_logic;
signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc : std_logic;
signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned (4 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
......@@ -158,12 +158,12 @@ architecture rtl of WF_tx_serializer is
--=================================================================================================
-- architecture begin
--=================================================================================================
--=================================================================================================
begin
--! The signal tx_clk_p_buff_i is used for the synchronization of the state transitions of the
--! machine as well as of the actions on the output signals.
--! machine as well as of the actions on the output signals.
-- The following drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock).
......@@ -177,29 +177,29 @@ begin
--! A new bit is delivered after the assertion of tx_clk_p_buff (1).
--! The counter Outgoing_Bits_Index that keeps the index of a bit being delivered is updated after
--! The counter Outgoing_Bits_Index that keeps the index of a bit being delivered is updated after
--! the delivery of the bit, after the tx_clk_p_buff (3) assertion. The counter is ahead of the
--! bit being sent.
--! In the sending_bytes state, where the unit is expecting data bytes from the
--! In the sending_bytes state, where the unit is expecting data bytes from the
--! WF_prod_bytes_retriever, the unit delivers a request for a new byte after the tx_clk_p_buff (0)
--! assertion, when the Outgoing_Bits_Index counter is empty (which means that the last bit of a
--! assertion, when the Outgoing_Bits_Index counter is empty (which means that the last bit of a
--! previous byte is now being delivered).
--! The WF_engine_control responds to the request by sending a new address to the
--! WF_prod_bytes_retriever for the retreival of a byte from the memory or the stand-alone bus.
--! The WF_engine_control responds to the request by sending a new address to the
--! WF_prod_bytes_retriever for the retreival of a byte from the memory or the stand-alone bus.
--! The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request,
--! and starts being transmitted at the tx_clk_p_buff (1) of the next FD_TXCK cycle.
---------------------------------------------------------------------------------------------------
-- Serializer's FSM --
---------------------------------------------------------------------------------------------------
--!@brief Serializer's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--!@brief Serializer's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow.
--! follow.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Serializer_FSM_Sync:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Serializer_FSM_Sync:
Serializer_FSM_Sync: process (uclk_i)
begin
......@@ -212,16 +212,15 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Serializer_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Serializer_FSM_Comb_State_Transitions
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
s_session_timedout,tx_start_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
case tx_state is
case tx_state is
when idle =>
if tx_start_p_i = '1' then
......@@ -232,9 +231,9 @@ begin
when sync_to_txck =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
......@@ -244,7 +243,7 @@ begin
when send_fss =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
elsif s_session_timedout = '1' then
......@@ -268,42 +267,42 @@ begin
when send_crc_bytes =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_clk_p_buff_i(3), to get the 31 as top value
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
else
nx_tx_state <= send_crc_bytes;
end if;
when send_fes =>
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_clk_p_buff_i(3) to get the 15 as top value
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_state <= idle;
else
nx_tx_state <= send_fes;
end if;
else
nx_tx_state <= send_fes;
end if;
when stop_transmission =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_state <= idle;
else
nx_tx_state <= stop_transmission;
end if;
end if;
when others =>
......@@ -312,16 +311,15 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Serializer_FSM_Comb_Output_Signals: definition of the output
--! signals of the FSM
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process Serializer_FSM_Comb_Output_Signals
Serializer_FSM_Comb_Output_Signals: process ( tx_state )
begin
case tx_state is
case tx_state is
when idle | sync_to_txck =>
when idle | sync_to_txck =>
---------------------------------
s_prepare_to_produce <= '1';
......@@ -345,7 +343,7 @@ begin
s_stop_transmission <= '0';
when send_data_byte =>
when send_data_byte =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -360,7 +358,7 @@ begin
when send_crc_bytes =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
---------------------------------
s_sending_crc <= '1';
......@@ -369,7 +367,7 @@ begin
s_stop_transmission <= '0';
when send_fes =>
when send_fes =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -386,15 +384,15 @@ begin
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
---------------------------------
s_stop_transmission <= '1';
---------------------------------
when others =>
when others =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
......@@ -417,11 +415,11 @@ Input_Byte_Retrieval: process (uclk_i)
if nfip_rst_i = '1' then
s_byte <= (others => '0');
else
else
if byte_request_accept_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
......@@ -436,35 +434,35 @@ Input_Byte_Retrieval: process (uclk_i)
s_data_byte_manch <= f_manch_encoder (s_byte);
s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes);
---------------------------------------------------------------------------------------------------
-- CRC calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the CRC unit
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the CRC unit
crc_generation: WF_crc
crc_generation: WF_crc
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_ok_p_o => open,
crc_ok_p_o => open,
-------------------------------------------------
crc_o => s_crc_bytes);
-------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
s_start_crc_p <= s_sending_fss and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- the CRC calculation starts when at the end of th e FSS (beginning of data bytes delivery)
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
......@@ -475,13 +473,13 @@ Input_Byte_Retrieval: process (uclk_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Managment of the pointer that indicates which bit of a manchester encoded byte is to be
--! delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a
--! CRC or a FES byte.
--! CRC or a FES byte.
Outgoing_Bits_Index: WF_decr_counter
generic map (g_counter_lgth => 5)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
......@@ -491,7 +489,7 @@ Input_Byte_Retrieval: process (uclk_i)
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets the values to the
-- Outgoing_Bits_Index inputs.
......@@ -500,10 +498,10 @@ Input_Byte_Retrieval: process (uclk_i)
begin
if s_prepare_to_produce ='1' then
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '1';
s_decr_index_p <= '0';
elsif s_sending_fss = '1' then -- sending the 16 FSS manch. bits
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
......@@ -518,19 +516,19 @@ Input_Byte_Retrieval: process (uclk_i)
elsif s_sending_crc = '1' then -- sending the 32 manch. CRC bits
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_fes = '1' then -- sending the 16 manch. FSS
s_bit_index_top <= to_unsigned (c_FES'length - 1, s_bit_index'length);
s_bit_index_top <= to_unsigned (c_FES'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
else
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '0';
s_decr_index_p <= '0';
......@@ -538,7 +536,7 @@ Input_Byte_Retrieval: process (uclk_i)
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the unit that according to the state of the FSM and the
--! bits index counter, outputs FSS, data, CRC or FES manchester encoded bits to the txd_o.
--! The unit also generates the tx_enable_o signal.
......@@ -546,19 +544,19 @@ Input_Byte_Retrieval: process (uclk_i)
bits_to_txd: WF_bits_to_txd
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_fss,
sending_data_i => s_sending_data,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_fes,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
---------------------------------------------
txd_o => s_txd,
tx_enable_o => s_tx_enable);
txd_o => s_txd,
tx_enable_o => tx_enable_o);
---------------------------------------------
......@@ -592,8 +590,6 @@ Input_Byte_Retrieval: process (uclk_i)
tx_data_o <= s_txd;
tx_enable_o <= s_tx_enable;
tx_osc_rst_p_o <= s_session_timedout;
byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
......@@ -606,4 +602,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_wb_controller.vhd
View file @ 297713da
......@@ -11,7 +11,7 @@
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
......@@ -27,8 +27,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
--! the user's STBs.
--! @brief The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
--! the user's STBs.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01
--
--
--! @details \n
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_production \n
......@@ -57,10 +57,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -71,7 +71,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_wb_controller is
port (
-- INPUTS
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset
......@@ -122,25 +122,25 @@ begin
s_wb_we_synch <= (others => '0');
else
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_write_p_o: Generation of the wb_ack_write_p signal
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
--! The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010"))
else '0';
......@@ -152,7 +152,7 @@ begin
--! The 1 wb_clk-wide pulse is generated if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00"))
......@@ -160,17 +160,17 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Output_Register
--!@brief Output_Register
WB_ACK: process (wb_clk_i)
WB_ACK: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
wb_ack_p_o <= '0';
wb_ack_prod_p_o <= '0';
else
wb_ack_p_o <= s_wb_ack_read_p or s_wb_ack_write_p;
wb_ack_prod_p_o <= s_wb_ack_write_p;
else
wb_ack_p_o <= s_wb_ack_read_p or s_wb_ack_write_p;
wb_ack_prod_p_o <= s_wb_ack_write_p;
end if;
end if;
end process;
......
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