masterFIP
Overview
WorldFIP is a
fieldbus widely used at CERN; there are more than 10’000 WorldFIP nodes
installed all around the LHC.
WorldFIP is used to connect critical sensors and actuators (by equipment
groups like Power Converters, Cryogenics, Beam Instrumentation etc) with
the control and supervision level.
The WorldFIP nodes are radiation-tolerant and are installed close the
LHC magnets. The WorldFIP masters are always installed in radiation safe
zones. One master is managing typically around 50 nodes.
The signal of the bus is 5V
differential.
We used to purchase the WorldFIP masters and the nodes by the company
Alstom. However Alstom has been gradually
stopping all the WorldFIP support, as new Ethernet based solutions are
now dominant.
At CERN we need to provide WorldFIP support until at least 2035, the
end-of-life of the HL-LHC as it would be very costly to change all the
cabling and the equipment to another radiation-tolerant solution.
The fact that there is no more WorldFIP support by Alstom is the main
reason for the design and support our own WorldFIP equipment at CERN.
The migration of the all the 500 Alstom masters to the new masterFIP
is targeted for the end of 2018, CERN's Long Shutdown 2.
The project has been developed following the Functional Specifications and provides a complete replacement of the Alstom solution for CERN applications. It is divided into four sub-projects:
- Hardware : Mezzanine board schematic and layout, to be combined with a SPEC carrier
- Gateware : HDL design with Mock Turtle
- Software : Bare-metal C code running in the FPGA-embedded Mock Turtle CPUs, library and tools.
- Testing : Production and functional tests.
Specifications
Parameter | Value |
Form factor |
LPC FMC mezzanine on SPEC PCIe carrier The board could be plugged on a different carrier, but the supported gw/sw/lib are for SPEC |
WorldFIP services |
Periodic variables production/consumption Aperiodic unacknowledged messages production/consumption Aperiodic acknowledged messages consumption Aperiodic SMMPS variables production/consumption |
Supported WorldFIP bitrates | 31.25Kbps, 1Mbps, 2.5Mbps The FMC supports 5Mbps, but it has not been tested |
Front panel connectors |
Micro D-Sub 9 for WorldFIP Lemo 00 for input synchronization pulse; sw selectable 50 Ohm termination |
Synchronization | Upon a sync pulse from the Lemo, a new macrocycle starts after few us |
Front panel LEDs |
FMC TX ACT : at the end of a macrocycle there has been no transmission failure FMC TX ERR: at the end of a macrocycle transmission errors have been detected FMC RX ACT: at the end of a macrocycle there has been no reception failure FMC RX ERR: at the end of a macrocycle reception errors have been detected FMC SYNC ACT: application expects sync pulse and it is receiving it successfully FMC SYNC ERR: application expects sync pulse which it is not arriving SPEC GREEN: blinking using the 100 MHz clock SPEC RED: PCIe reset |
Test points | Four through hole test points (TP) next to the FMC connector TP1: connected to FielDrive RXD TP2: connected to FielDrive TXD TP3: connected to Mock Turtle leds and debug reg bit 8 TP4: connected to Mock Turtle leds and debug reg bit 9 |
Full details in the Functional Specifications document.
Release
Release | ID | Release Date | Comments |
[Current Release](https://www.ohwr.org/project/masterfip/wikis/current-release) | v1.1.0 | Feb 2018 | At CERN operational installations since Feb 2018 |
Next-release-under-evaluation | v1.1.1 | May 2018 | Corrections on sw code regarding only macrocycle reloading (for BI application) |
URV-release-under-evaluation | v1.2.0 | expected in Jun 2018 | New Mock Turtle with URV; under solderpad lic |
Project info
- Sub-projects:
- Work Packages
- Functional Specification
- Design Guide
- masterFIP Users
- Project Presentation (CERN only)
- Developers' wikis (CERN only)
Project Status
Date | Event |
07-2014 | Evaluation of needs and of the available solutions; definition of the work packages |
12-2014 | MasterFIP functional specification ready |
06-2015 | Working hard on driver development and gateware for the masterFIP. |
10-2015 | First firmware commit using the Mock Turtle core; basic communication with nanoFIP and microFIP agents |
01-2016 | Starting of collaboration with Creotech for the PTS |
05-2016 | Solved well-hidden bug in GN4124-core that was crashing the masterFIP applications when 2 boards were installed in a Kontron PCI762 |
07-2016 | 1-month runs with Cryo lab equipment run smoothly and the migration to masterFIP was transparent to the cryo users! |
08-2016 | Creotech delivers PTS |
09-2016 | Successful migration of the RadMon application to the masterFIP |
10-2016 | Hardware V2 ready for review |
11-2016 | Startup of collaboration with QPS for the migration of their application |
01-2017 | Hardware V3 ready for production; no ADC diagnostics on the board based on high production and maintenance costs |
28-03-2017 | 15 V3 prototype cards received; validated and they are ok! |
19-04-2017 | Successful migration of the FGC2 application to the masterFIP |
30-08-2017 | Long runs in lab of equipment groups |
06-09-2017 | Production of 130 v4 masterFIP boards started, to be available by early December 2017 |
12-12-2017 | First installation of 51 modules in the LHC |
Contacts
Erik van der Bij | Eva Gousiou | Michel Arruat | Julien Palluel
E.Gousiou, E.Van der Bij, 6 September 2017