... | ... | @@ -9,11 +9,11 @@ the following table: |
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|[WP1](WP1)|**Scope, objectives, resources, budget** definition; evaluation of the **Strukton solution**|[Done](https://www.ohwr.org/project/masterfip/uploads/d2e6fadb19f962b82f93972daf1f06b8/masterFIP_technical_choice.pdf)|
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|[WP2](WP2)|**Functional specification** drafting|[Done](https://www.ohwr.org//edms.cern.ch/ui/#!master/navigator/document?d:1938176066:1938176066:subdocs)|
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|[WP3](WP3)|**Gateware**: writing of VHDL code or extending Strukton code|[Done](https://www.ohwr.org/project/masterfip-gw/wiki)|
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|[WP4](WP4)|**Gateware testing**: VHDL Testbench|In progress|
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|[WP4](WP4)|**Gateware testing**: VHDL Testbench|[Done](https://ohwr.org/project/masterfip-gw/tree/tom-systemverilog-testbench)|
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|[WP5](WP5)|**Hardware**: design FMC mezzanine|[Done](https://www.ohwr.org/project/fmc-masterfip/wiki)|
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|[WP6](WP6)|**Hardware testing**: Production test Suite of the FMC mezzanine|[Done](https://www.ohwr.org/project/masterfip-tst/wiki)|
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|[WP7](WP7)|**Software**: writing of drivers/ libraries; evaluation of the **Strukton solution**|[Done](https://www.ohwr.org/project/masterfip-sw/wiki)|
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|[WP8](WP8)|**Testing**: testing of the combined hardware, gateware, software|In progress|
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|[WP8](WP8)|**Testing**: testing of the combined hardware, gateware, software|[Done](https://edms.cern.ch/ui/#!master/navigator/document?P:100035470:100048504:subDocs)|
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