... | ... | @@ -25,9 +25,7 @@ then type *vers*: |
|
|
## Source code
|
|
|
|
|
|
- **HW**: for
|
|
|
[EDA-03098-V3](https://www.ohwr.org//edms.cern.ch/project/EDA-03098)
|
|
|
and
|
|
|
[EDA-03098-V4](https://www.ohwr.org//edms.cern.ch/project/EDA-03098)
|
|
|
[EDA-03098-V4](https://edms.cern.ch/project/EDA-03098)
|
|
|
boards
|
|
|
- **GW**: FPGA v2.0.0 [source
|
|
|
code](https://www.ohwr.org/project/masterfip-gw/tree/master?utf8=%E2%9C%93&rev=v2.0.0&branch=master&tag=v2.0.0)
|
... | ... | |