... | ... | @@ -53,30 +53,13 @@ applications. It is divided into four sub-projects: |
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|**Parameter**|**Value**|
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|----|----|
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|Form factor|**LPC** FMC mezzanine on SPEC **PCIe** carrier
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The board could be plugged on a different carrier, but the supported gw/sw/lib are for SPEC|
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|WorldFIP services|**Periodic variables** production/consumption
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**Aperiodic unacknowledged messages** production/consumption
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**Aperiodic acknowledged messages** consumption
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**Aperiodic SMMPS variables** production/consumption|
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|Supported WorldFIP bitrates|31.25Kbps, 1Mbps, 2.5Mbps
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The FMC supports 5Mbps, but it has not been tested|
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|Front panel connectors|**Micro D-Sub 9** for WorldFIP
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**Lemo 00** for input synchronization pulse; sw selectable 50 Ohm termination|
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|Form factor|**LPC** FMC mezzanine on SPEC **PCIe** carrier<br>The board could be plugged on a different carrier, but the supported gw/sw/lib are for SPEC|
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|WorldFIP services|**Periodic variables** production/consumption<br>**Aperiodic unacknowledged messages** production/consumption<br>**Aperiodic acknowledged messages** consumption<br>**Aperiodic SMMPS variables** production/consumption|
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|Supported WorldFIP bitrates|31.25Kbps, 1Mbps, 2.5Mbps<br>The FMC supports 5Mbps, but it has not been tested|
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|Front panel connectors|**Micro D-Sub 9** for WorldFIP<br>**Lemo 00** for input synchronization pulse; sw selectable 50 Ohm termination|
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|Synchronization|Upon a sync pulse from the Lemo, a new macrocycle starts after few us; [jitter ~ 100 ns](https://wikis.cern.ch/display/TEEPCCCE/FGClite+migration+from+CC144+to+MasterFIP+gateways)|
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|Front panel LEDs|**FMC TX ACT** : at the end of a macrocycle there has been no transmission failure
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**FMC TX ERR**: at the end of a macrocycle transmission errors have been detected
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**FMC RX ACT**: at the end of a macrocycle there has been no reception failure
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**FMC RX ERR**: at the end of a macrocycle reception errors have been detected
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**FMC SYNC ACT**: application expects sync pulse and it is receiving it successfully
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**FMC SYNC ERR**: application expects sync pulse which it is not arriving
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**SPEC GREEN**: blinking using the 100 MHz clock
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**SPEC RED**: PCIe reset|
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|Test points|Four through hole test points (TP) next to the FMC connector
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**TP1**: connected to FielDrive RXD
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**TP2**: connected to FielDrive TXD
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**TP3**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 8
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**TP4**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 9|
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|Front panel LEDs|**FMC TX ACT** : at the end of a macrocycle there has been no transmission failure<br>**FMC TX ERR**: at the end of a macrocycle transmission errors have been detected<br>**FMC RX ACT**: at the end of a macrocycle there has been no reception failure<br>**FMC RX ERR**: at the end of a macrocycle reception errors have been detected<br>**FMC SYNC ACT**: application expects sync pulse and it is receiving it successfully<br>**FMC SYNC ERR**: application expects sync pulse which it is not arriving<br>**SPEC GREEN**: blinking using the 100 MHz clock<br>**SPEC RED**: PCIe reset|
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|Test points|Four through hole test points (TP) next to the FMC connector<br>**TP1**: connected to FielDrive RXD<br>**TP2**: connected to FielDrive TXD<br>**TP3**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 8<br>**TP4**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 9|
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Full details in the [Functional
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... | ... | @@ -91,7 +74,7 @@ document. |
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|----|----|----|----|
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|**[Current Release](https://www.ohwr.org/project/masterfip/wikis/current-release)**|v1.1.0|Feb 2018|At CERN operational installations since Feb 2018|
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|**[Next-release-under-evaluation](Next-release-under-evaluation)**|v1.1.1|May 2018|Corrections on sw code regarding only macrocycle reloading (for BI application)|
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|**[URV-release-under-evaluation](URV-release-under-evaluation)**|v1.2.0|expected in Jun 2018|New Mock Turtle with URV; under solderpad lic|
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|**[URV-release-under-evaluation](URV-release-under-evaluation)**|v1.2.0|expected in 2020|New Mock Turtle with URV; under solderpad lic|
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... | ... | @@ -126,7 +109,7 @@ document. |
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## Project Status
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|**Date**|**Event**|
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|----|----|
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|--------|---------|
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|07-2014|Evaluation of needs and of the available solutions; definition of the [work packages](WorkPackages)|
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|12-2014|MasterFIP [functional specification](https://edms.cern.ch/document/1457263) ready|
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|06-2015|Working hard on driver development and gateware for the masterFIP.|
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... | ... | @@ -139,13 +122,17 @@ document. |
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|10-2016|**Hardware V2** ready for review|
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|11-2016|Startup of collaboration with **QPS** for the migration of their application|
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|01-2017|**Hardware V3** ready for production; no ADC diagnostics on the board based on high production and maintenance costs|
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|28-03-2017|15 V3 prototype cards received; validated and they are ok!|
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|19-04-2017|Successful migration of the **FGC2** application to the masterFIP|
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|30-08-2017|Long runs [in lab of equipment groups](/masterfip-users#in-lab)|
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|06-09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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|12-12-2017|First installation of 51 modules in the LHC|
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|08-01-2018|Requested production of 600 masterFIP boards.|
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|30-05-2018|Received of 100 masterFIP boards. Remaining 500 expected end June|
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|03-2017|15 V3 prototype cards received; validated and they are ok!|
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|04-2017|Successful migration of the **FGC2** application to the masterFIP|
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|08-2017|Long runs [in lab of equipment groups](/masterfip-users#in-lab)|
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|09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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|12-2017|First installation of 51 modules in the LHC|
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|01-2018|Requested production of 600 masterFIP boards|
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|02-2018|Validation of the design in the LHC|
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|05-2018|Received of 100 masterFIP boards. Remaining 500 expected end June|
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|07-2018|Reception of 500 v4 masterFIP boards|
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|02-2020|500 boards being installed in the LHC for different equipment groups like Power-Converters, Quench-Protection, Cryogenics|
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... | ... | @@ -161,6 +148,4 @@ Palluel](mailto:julien.palluel@cern.ch) |
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-----
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*E.Gousiou, E.Van der Bij, 8 June 2018*
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