... | @@ -51,59 +51,33 @@ applications. It is divided into four sub-projects: |
... | @@ -51,59 +51,33 @@ applications. It is divided into four sub-projects: |
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## Specifications
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## Specifications
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<table>
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|**Parameter**|**Value**|
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<tbody>
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|----|----|
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<tr class="odd">
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|Form factor|**LPC** FMC mezzanine on SPEC **PCIe** carrier
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<td><strong>Parameter</strong></td>
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The board could be plugged on a different carrier, but the supported gw/sw/lib are for SPEC|
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<td><strong>Value</strong></td>
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|WorldFIP services|**Periodic variables** production/consumption
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</tr>
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**Aperiodic unacknowledged messages** production/consumption
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<tr class="even">
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**Aperiodic acknowledged messages** consumption
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<td>Form factor</td>
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**Aperiodic SMMPS variables** production/consumption|
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<td><strong>LPC</strong> FMC mezzanine on SPEC <strong>PCIe</strong> carrier<br />
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|Supported WorldFIP bitrates|31.25Kbps, 1Mbps, 2.5Mbps
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The board could be plugged on a different carrier, but the supported gw/sw/lib are for SPEC</td>
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The FMC supports 5Mbps, but it has not been tested|
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</tr>
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|Front panel connectors|**Micro D-Sub 9** for WorldFIP
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<tr class="odd">
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**Lemo 00** for input synchronization pulse; sw selectable 50 Ohm termination|
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<td>WorldFIP services</td>
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|Synchronization|Upon a sync pulse from the Lemo, a new macrocycle starts after few us|
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<td><strong>Periodic variables</strong> production/consumption<br />
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|Front panel LEDs|**FMC TX ACT** : at the end of a macrocycle there has been no transmission failure
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<strong>Aperiodic unacknowledged messages</strong> production/consumption<br />
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**FMC TX ERR**: at the end of a macrocycle transmission errors have been detected
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<strong>Aperiodic acknowledged messages</strong> consumption<br />
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**FMC RX ACT**: at the end of a macrocycle there has been no reception failure
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<strong>Aperiodic SMMPS variables</strong> production/consumption</td>
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**FMC RX ERR**: at the end of a macrocycle reception errors have been detected
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</tr>
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**FMC SYNC ACT**: application expects sync pulse and it is receiving it successfully
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<tr class="even">
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**FMC SYNC ERR**: application expects sync pulse which it is not arriving
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<td>Supported WorldFIP bitrates</td>
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**SPEC GREEN**: blinking using the 100 MHz clock
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<td>31.25Kbps, 1Mbps, 2.5Mbps<br />
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**SPEC RED**: PCIe reset|
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The FMC supports 5Mbps, but it has not been tested</td>
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|Test points|Four through hole test points (TP) next to the FMC connector
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</tr>
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**TP1**: connected to FielDrive RXD
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<tr class="odd">
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**TP2**: connected to FielDrive TXD
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<td>Front panel connectors</td>
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**TP3**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 8
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<td><strong>Micro D-Sub 9</strong> for WorldFIP<br />
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**TP4**: connected to Mock Turtle [leds and debug](https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html) reg bit 9|
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<strong>Lemo 00</strong> for input synchronization pulse; sw selectable 50 Ohm termination</td>
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</tr>
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<tr class="even">
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<td>Synchronization</td>
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<td>Upon a sync pulse from the Lemo, a new macrocycle starts after few us</td>
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</tr>
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<tr class="odd">
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<td>Front panel LEDs</td>
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<td><strong>FMC TX ACT</strong> : at the end of a macrocycle there has been no transmission failure<br />
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<strong>FMC TX ERR</strong>: at the end of a macrocycle transmission errors have been detected<br />
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<strong>FMC RX ACT</strong>: at the end of a macrocycle there has been no reception failure<br />
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<strong>FMC RX ERR</strong>: at the end of a macrocycle reception errors have been detected<br />
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<strong>FMC SYNC ACT</strong>: application expects sync pulse and it is receiving it successfully<br />
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<strong>FMC SYNC ERR</strong>: application expects sync pulse which it is not arriving<br />
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<strong>SPEC GREEN</strong>: blinking using the 100 MHz clock<br />
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<strong>SPEC RED</strong>: PCIe reset</td>
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</tr>
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<tr class="even">
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<td>Test points</td>
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<td>Four through hole test points (TP) next to the FMC connector<br />
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<strong>TP1</strong>: connected to FielDrive RXD<br />
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<strong>TP2</strong>: connected to FielDrive TXD<br />
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<strong>TP3</strong>: connected to Mock Turtle <a href="https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html">leds and debug</a> reg bit 8<br />
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<strong>TP4</strong>: connected to Mock Turtle <a href="https://www.ohwr.org/project/masterfip-gw/commits/master/rtl/wbgen/masterfip_wbgen2_csr.html">leds and debug</a> reg bit 9</td>
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</tr>
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</tbody>
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</table>
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Full details in the [Functional
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Full details in the [Functional
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Specifications](https://www.ohwr.org//edms.cern.ch/ui/#!master/navigator/document?d:1938176066:1938176066:subdocs)
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Specifications](https://www.ohwr.org//edms.cern.ch/ui/#!master/navigator/document?d:1938176066:1938176066:subdocs)
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... | @@ -113,34 +87,12 @@ document. |
... | @@ -113,34 +87,12 @@ document. |
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## Release
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## Release
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<table>
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|**Release**|**ID**|**Release Date**|**Comments**|
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<tbody>
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|----|----|----|----|
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<tr class="odd">
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|**[Current Release](https://www.ohwr.org/project/masterfip/wikis/current-release)**|v1.1.0|Feb 2018|At CERN operational installations since Feb 2018|
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<td><strong>Release</strong></td>
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|**[Next-release-under-evaluation](Next-release-under-evaluation)**|v1.1.1|May 2018|Corrections on sw code regarding only macrocycle reloading (for BI application)|
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<td><strong>ID</strong></td>
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|**[URV-release-under-evaluation](URV-release-under-evaluation)**|v1.2.0|expected in Jun 2018|New Mock Turtle with URV; under solderpad lic|
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<td><strong>Release Date</strong></td>
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<td><strong>Comments</strong></td>
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</tr>
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<tr class="even">
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<td><strong>[Current Release](https://www.ohwr.org/project/masterfip/wikis/current-release)</strong></td>
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<td>v1.1.0</td>
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<td>Feb 2018</td>
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<td>At CERN operational installations since Feb 2018</td>
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</tr>
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<tr class="odd">
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<td><strong>[Next-release-under-evaluation](Next-release-under-evaluation)</strong></td>
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<td>v1.1.1</td>
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<td>May 2018</td>
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<td>Corrections on sw code regarding only macrocycle reloading (for BI application)</td>
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</tr>
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<tr class="even">
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<td><strong>[URV-release-under-evaluation](URV-release-under-evaluation)</strong></td>
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<td>v1.2.0</td>
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<td>expected in Jun 2018</td>
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<td>New Mock Turtle with URV; under solderpad lic</td>
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</tr>
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</tbody>
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</table>
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-----
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-----
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... | @@ -173,90 +125,28 @@ document. |
... | @@ -173,90 +125,28 @@ document. |
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## Project Status
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## Project Status
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<table>
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|**Date**|**Event**|
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<tbody>
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|----|----|
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<tr class="odd">
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|07-2014|Evaluation of needs and of the available solutions; definition of the [work packages](WorkPackages)|
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<td><strong>Date</strong></td>
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|12-2014|MasterFIP [functional specification](https://edms.cern.ch/document/1457263) ready|
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<td><strong>Event</strong></td>
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|06-2015|Working hard on driver development and gateware for the masterFIP.|
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</tr>
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|10-2015|First firmware commit using the **Mock Turtle core**; **basic communication** with nanoFIP and microFIP agents|
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<tr class="even">
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|01-2016|Starting of collaboration with Creotech for the **PTS**|
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<td>07-2014</td>
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|05-2016|Solved well-hidden **bug in GN4124-core** that was crashing the masterFIP applications when 2 boards were installed in a Kontron PCI762|
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<td>Evaluation of needs and of the available solutions; definition of the [work packages](WorkPackages)</td>
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|07-2016|1-month runs with **Cryo** lab equipment run smoothly and the migration to masterFIP was transparent to the cryo users!|
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</tr>
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|08-2016|Creotech **delivers PTS**|
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<tr class="odd">
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|09-2016|Successful migration of the **RadMon** application to the masterFIP|
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<td>12-2014</td>
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|10-2016|**Hardware V2** ready for review|
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<td>MasterFIP <a href="https://edms.cern.ch/document/1457263">functional specification</a> ready</td>
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|11-2016|Startup of collaboration with **QPS** for the migration of their application|
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</tr>
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|01-2017|**Hardware V3** ready for production; no ADC diagnostics on the board based on high production and maintenance costs|
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<tr class="even">
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|28-03-2017|15 V3 prototype cards received; validated and they are ok!|
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<td>06-2015</td>
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|19-04-2017|Successful migration of the **FGC2** application to the masterFIP|
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<td>Working hard on driver development and gateware for the masterFIP.</td>
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|30-08-2017|Long runs [in lab of equipment groups](/masterfip-users#in-lab)|
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</tr>
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|06-09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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<tr class="odd">
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|12-12-2017|First installation of 51 modules in the LHC|
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<td>10-2015</td>
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|08-01-2018|Requested production of 600 masterFIP boards.|
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<td>First firmware commit using the <strong>Mock Turtle core</strong>; <strong>basic communication</strong> with nanoFIP and microFIP agents</td>
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|30-05-2018|Received of 100 masterFIP boards. Remaining 500 expected end June|
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</tr>
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<tr class="even">
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<td>01-2016</td>
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<td>Starting of collaboration with Creotech for the <strong>PTS</strong></td>
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</tr>
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<tr class="odd">
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<td>05-2016</td>
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<td>Solved well-hidden <strong>bug in GN4124-core</strong> that was crashing the masterFIP applications when 2 boards were installed in a Kontron PCI762</td>
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</tr>
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<tr class="even">
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<td>07-2016</td>
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<td>1-month runs with <strong>Cryo</strong> lab equipment run smoothly and the migration to masterFIP was transparent to the cryo users!</td>
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</tr>
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<tr class="odd">
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<td>08-2016</td>
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<td>Creotech <strong>delivers PTS</strong></td>
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</tr>
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<tr class="even">
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<td>09-2016</td>
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<td>Successful migration of the <strong>RadMon</strong> application to the masterFIP</td>
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</tr>
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<tr class="odd">
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<td>10-2016</td>
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<td><strong>Hardware V2</strong> ready for review</td>
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</tr>
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<tr class="even">
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<td>11-2016</td>
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<td>Startup of collaboration with <strong>QPS</strong> for the migration of their application</td>
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</tr>
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<tr class="odd">
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<td>01-2017</td>
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<td><strong>Hardware V3</strong> ready for production; no ADC diagnostics on the board based on high production and maintenance costs</td>
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</tr>
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<tr class="even">
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<td>28-03-2017</td>
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<td>15 V3 prototype cards received; validated and they are ok!</td>
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</tr>
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<tr class="odd">
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<td>19-04-2017</td>
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<td>Successful migration of the <strong>FGC2</strong> application to the masterFIP</td>
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</tr>
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<tr class="even">
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<td>30-08-2017</td>
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<td>Long runs [in lab of equipment groups](/masterfip-users#in-lab)</td>
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</tr>
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<tr class="odd">
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<td>06-09-2017</td>
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<td>Production of 130 v4 masterFIP boards started, to be available by early December 2017</td>
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</tr>
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<tr class="even">
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<td>12-12-2017</td>
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<td>First installation of 51 modules in the LHC</td>
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</tr>
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<tr class="odd">
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<td>08-01-2018</td>
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<td>Requested production of 600 masterFIP boards.</td>
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</tr>
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<tr class="even">
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<td>30-05-2018</td>
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<td>Received of 100 masterFIP boards. Remaining 500 expected end June</td>
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</tr>
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</tbody>
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</table>
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-----
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... | @@ -273,3 +163,4 @@ Palluel](mailto:julien.palluel@cern.ch) |
... | @@ -273,3 +163,4 @@ Palluel](mailto:julien.palluel@cern.ch) |
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*E.Gousiou, E.Van der Bij, 8 June 2018*
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*E.Gousiou, E.Van der Bij, 8 June 2018*
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