... | @@ -19,11 +19,9 @@ At CERN though we need to provide WorldFIP support until at least 2035, |
... | @@ -19,11 +19,9 @@ At CERN though we need to provide WorldFIP support until at least 2035, |
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the end-of-life of the HL-LHC as it would be very costly to change all
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the end-of-life of the HL-LHC as it would be very costly to change all
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the cabling and the equipment to another Ethernet-based solution.
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the cabling and the equipment to another Ethernet-based solution.
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The fact that there is no more WorldFIP support by Alstom is the main
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The fact that there is no more WorldFIP support by Alstom is the main
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reason we need to design and support our own WorldFIP equipment at
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reason we need to design and support our own WorldFIP equipment at CERN.
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CERN.
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The masterFIP board, is a WorldFIP master, the replacement of the Alstom
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The masterFIP board, is a WorldFIP master, the replacement of the Alstom
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WorldFIP master board.
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WorldFIP master board. It is an [FMC
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It is an [FMC
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mezzanine](https://www.ohwr.org/project/fmc-worldfip/wiki), to be
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mezzanine](https://www.ohwr.org/project/fmc-worldfip/wiki), to be
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combined with a [SPEC PCI
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combined with a [SPEC PCI
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Express](https://www.ohwr.org/project/spec/wiki) carrier.
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Express](https://www.ohwr.org/project/spec/wiki) carrier.
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... | @@ -37,13 +35,11 @@ catalog |
... | @@ -37,13 +35,11 @@ catalog |
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\- FielDrive chip, that is a WorldFIP line driver; we still purchase
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\- FielDrive chip, that is a WorldFIP line driver; we still purchase
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this component from Alstom as it will remain available in their catalog
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this component from Alstom as it will remain available in their catalog
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\- ADC that is acting as an on-board-oscilloscope when needed
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\- Input for an external synchronization pulse that can trigger the
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startup of WorldFIP communication
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\- One Wire temperature and ID chip, as in all our projects
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\- EEPROM, as in all our FMC projects
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\- One Wire temperature-and-ID-chip, as in all our FMC projects
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\- EEPROM, as in all our projects
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\- Input for an external synchronization pulse (that is usually
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triggering the startup of WorldFIP communication)
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The project is divided into four sub-projects:
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The project is divided into four sub-projects:
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... | @@ -81,44 +77,40 @@ Please refer to the corresponding sub-project for detailed information. |
... | @@ -81,44 +77,40 @@ Please refer to the corresponding sub-project for detailed information. |
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<td>Working hard on driver development and gateware for the masterFIP.</td>
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<td>Working hard on driver development and gateware for the masterFIP.</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>08-10-2015</td>
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<td>10-2015</td>
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<td>First firmware commit using the Mock Turtle core</td>
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<td>First firmware commit using the <strong>Mock Turtle core</strong>; <strong>basic communication</strong> with nanoFIP and microFIP agents</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>24-10-2015</td>
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<td>01-2016</td>
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<td>Basic communication with nanoFIP and microFIP agents</td>
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<td>Starting of collaboration with Creotech for the <strong>PTS</strong></td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>12-01-2016</td>
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<td>05-2016</td>
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<td>Starting of collaboration with Creotech for the PTS</td>
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<td>Solved well-hidden <strong>bug in GN4124-core</strong> that was crashing the masterFIP applications when 2 boards were installed in a Kontron PCI762</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
|
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<td>25-05-2016</td>
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<td>07-2016</td>
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<td>Solved well-hidden bug in GN4124-core that was crashing the masterFIP applications when 2 boards were installed in a Kontron PCI762</td>
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<td>1-month runs with <strong>Cryo</strong> lab equipment run smoothly and the migration to masterFIP was transparent to the cryo users!</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
|
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<td>10-07-2016</td>
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<td>08-2016</td>
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<td>1-month long runs with cryo lab equipment run smoothly and the migration to masterFIP was transparent to the cryo users!</td>
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<td>Creotech <strong>delivers PTS</strong></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
|
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<td>27-07-2016</td>
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<td>09-2016</td>
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<td>Creotech delivers PTS</td>
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<td>Successful migration of the <strong>RadMon</strong> application to the masterFIP</td>
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</tr>
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</tr>
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<tr class="odd">
|
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<tr class="odd">
|
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<td>06-09-2016</td>
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<td>10-2016</td>
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<td>Successful migration of the RadMon FESA class to the masterFIP</td>
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<td><strong>Hardware V2</strong> ready for review</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
|
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<td>01-10-2016</td>
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<td>11-2016</td>
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<td>V2 version of the hardware ready for review</td>
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<td>Startup of collaboration with <strong>QPS</strong> for the migration of their application</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>04-11-2016</td>
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<td>01-2017</td>
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<td>Startup of collaboration with QPS for thir migration</td>
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<td><strong>Hardware V3</strong> ready for production; no ADC diagnostics on the board based on high production and maintenance costs</td>
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</tr>
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<tr class="even">
|
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<td>30-01-2017</td>
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<td>Decision to remove the ADC diagnostics from the board; V3 version of the hardware ready for production</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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... | | ... | |