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MasterFIP - Gateware
Commit d8f12e4c authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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fixed writing part

parent dc166b67
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Showing with 78 additions and 49 deletions
rtl/spi_rmq_bridge.vhd
View file @ d8f12e4c
......@@ -66,7 +66,7 @@ architecture rtl of spi_rmq_bridge is
attribute fsm_encoding : string;
--! SPI FSM:
type t_SPI_STATE is (RX_SPI_HEADER, WR_RMQ, RD_RMQ, CS_DEASSERT);
type t_SPI_STATE is (RX_SPI_HEADER, PROCESSING, WR_RMQ, RD_RMQ, CS_DEASSERT);
signal s_spi_state : t_SPI_STATE;
attribute fsm_encoding of s_spi_state : signal is "one_hot";
......@@ -214,6 +214,7 @@ begin
when RX_SPI_HEADER =>
s_ready <= '0';
s_read_last <= '0';
s_data_valid <= '0';
if s_spi_cs_n = '0' then
if sample_en = '1' then
if s_rx_bit_c = 7 then
......@@ -222,14 +223,7 @@ begin
s_rx_shreg <= s_rx_shreg(g_data_width-2 downto 0) & s_spi_mosi;
if (s_rx_bit_c = g_data_width-1) then
s_rx_bit_c <= (others=>'0');
s_data_len <= s_rx_shreg(15 downto 8);
s_rmq_id <= s_rx_shreg(23 downto 16);
s_crtl_flags <= s_rx_shreg(31 downto 24);
if s_operation = '1' then
s_spi_state <= RD_RMQ;
else
s_spi_state <= WR_RMQ;
end if;
s_spi_state <= PROCESSING;
else
s_rx_bit_c <= s_rx_bit_c + 1;
s_spi_state <= RX_SPI_HEADER;
......@@ -241,38 +235,39 @@ begin
s_rx_shreg <= (others => '0');
s_tx_bit_c <= (others => '0');
s_rx_bit_c <= (others => '0');
s_data_len <= (others => '0');
s_rmq_id <= (others => '0');
s_crtl_flags <= (others => '0');
end if;
------------------------------------------
--when PROCESSING =>
-- if s_spi_cs_n = '0' then
-- if s_crtl_flags(0) = '0' then
-- s_wr_word_c <= s_wr_word_c + 1;
-- s_spi_state <= WR_RMQ;
-- else
-- s_spi_state <= RD_RMQ;
-- end if;
-- else
-- s_spi_state <= RX_SPI_HEADER;
-- end if;
when PROCESSING =>
if s_spi_cs_n = '0' then
s_data_len <= s_rx_shreg(15 downto 8);
s_rmq_id <= s_rx_shreg(23 downto 16);
if s_operation = '1' then
s_spi_state <= RD_RMQ;
else
s_spi_state <= WR_RMQ;
end if;
else
s_spi_state <= WR_RMQ;
end if;
------------------------------------------
when WR_RMQ =>
if s_spi_cs_n = '0' then
s_data_error <= '0';
s_data_valid <= '0';
s_data_header <= '0';
s_data_last <= '0';
if sample_en = '1' then
s_rx_shreg <= s_rx_shreg(g_data_width-2 downto 0) & s_spi_mosi;
if (s_rx_bit_c = g_data_width-1) then
s_rx_bit_c <= (others=>'0');
s_wr_word_c <= s_wr_word_c +1;
s_data_valid <= '1';
if s_wr_word_c = 1 then
if s_wr_word_c = 0 then
s_data_header <= '1';
s_spi_state <= WR_RMQ;
elsif s_wr_word_c = unsigned(s_data_len) then
elsif s_wr_word_c = unsigned(s_data_len)-1 then
s_data_last <= '1';
s_spi_state <= RX_SPI_HEADER;
else
......@@ -281,7 +276,6 @@ begin
s_spi_state <= WR_RMQ;
end if;
else
s_data_valid <= '0';
s_rx_bit_c <= s_rx_bit_c + 1;
s_wr_word_c <= s_wr_word_c;
s_spi_state <= WR_RMQ;
......@@ -344,35 +338,37 @@ begin
end if;
end process p_spi_fsm;
spi_miso_o <= s_tx_shreg(g_DATA_WIDTH-1);
----------------------------------------------------------------------------
--! RD RMQ FIFO
gen_miso_fifo: if g_CDC_ENABLE = 0 generate
cmp_output_fifo:entity work.inferred_sync_fifo
generic map (
g_data_width => g_DATA_WIDTH+1,
g_size => g_OUTPUT_FIFO_DEPTH,
g_show_ahead => true,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0,
g_register_flag_outputs => False
g_data_width => g_DATA_WIDTH+1,
g_size => g_OUTPUT_FIFO_DEPTH,
g_show_ahead => true,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0,
g_register_flag_outputs => False
)
port map(
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => s_miso_fifo_data_in,
we_i => s_miso_wr_en,
full_o => s_miso_fifo_wr_full,
q_o => s_miso_fifo_data_out,
empty_o => s_miso_fifo_rd_empty,
rd_i => s_miso_rd_en,
almost_empty_o => open,
almost_full_o => open,
count_o => open
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => s_miso_fifo_data_in,
we_i => s_miso_wr_en,
full_o => s_miso_fifo_wr_full,
q_o => s_miso_fifo_data_out,
empty_o => s_miso_fifo_rd_empty,
rd_i => s_miso_rd_en,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
end generate gen_miso_fifo;
......@@ -444,11 +440,16 @@ begin
s_mosi_header <= '0';
s_mosi_last <= '0';
s_mosi_error <= '0';
s_mosi_msb <= (others => '0');
s_mosi_lsb <= (others => '0');
s_mosi_wr_en <= '0';
s_wr_rmq_state <= IDLE;
else
case s_wr_rmq_state is
------------------------------------------
when IDLE =>
s_mosi_fifo_data_in <= (others => '0');
s_mosi_wr_en <= '0';
if s_data_valid = '1' then
s_mosi_msb <= s_rx_shreg(31 downto 16);
s_mosi_lsb <= s_rx_shreg(15 downto 0);
......@@ -457,12 +458,22 @@ begin
s_mosi_error <= s_data_error;
s_wr_rmq_state <= WR_MSB;
else
s_mosi_msb <= (others => '0');
s_mosi_lsb <= (others => '0');
s_mosi_header <= '0';
s_mosi_last <= '0';
s_mosi_error <= '0';
s_wr_rmq_state <= IDLE;
end if;
------------------------------------------
when WR_MSB =>
s_mosi_fifo_data_in <= s_mosi_header & '1' & s_mosi_last & s_mosi_error & x"0000" & s_mosi_msb;
s_mosi_fifo_data_in <= s_mosi_header & '1' & '0' & s_mosi_error & x"0000" & s_mosi_msb;
s_mosi_msb <= s_mosi_msb;
s_mosi_lsb <= s_mosi_lsb;
s_mosi_last <= s_mosi_last;
s_mosi_error <= s_mosi_error;
s_mosi_header <= s_mosi_header;
if s_mosi_fifo_wr_full = '0' then
s_mosi_wr_en <= '1';
s_wr_rmq_state <= WR_LSB;
......@@ -475,15 +486,32 @@ begin
when WR_LSB =>
s_mosi_fifo_data_in <= s_mosi_header & '1' & s_mosi_last & s_mosi_error & x"0000" & s_mosi_lsb;
if s_mosi_fifo_wr_full = '0' then
s_mosi_msb <= (others => '0');
s_mosi_lsb <= (others => '0');
s_mosi_header <= '0';
s_mosi_last <= '0';
s_mosi_error <= '0';
s_mosi_wr_en <= '1';
s_wr_rmq_state <= IDLE;
else
s_mosi_msb <= s_mosi_msb;
s_mosi_lsb <= s_mosi_lsb;
s_mosi_header <= s_mosi_header;
s_mosi_last <= s_mosi_last;
s_mosi_error <= s_mosi_error;
s_mosi_wr_en <= '0';
s_wr_rmq_state <= WR_LSB;
end if;
------------------------------------------
when others =>
s_mosi_fifo_data_in <= (others => '0');
s_mosi_msb <= (others => '0');
s_mosi_lsb <= (others => '0');
s_mosi_header <= '0';
s_mosi_last <= '0';
s_mosi_error <= '0';
s_mosi_wr_en <= '0';
s_wr_rmq_state <= IDLE;
end case;
......@@ -497,6 +525,7 @@ begin
g_data_width => g_DATA_WIDTH+4,
g_size => g_INPUT_FIFO_DEPTH,
g_show_ahead => true,
g_show_ahead_legacy_mode => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
......
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