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MasterFIP - Gateware
Commit a030d4f6 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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changed ise mapping parameters to meet constraints!

parent 100564c7
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rtl/fmc_masterFIP_core.vhd
View file @ a030d4f6
......@@ -167,7 +167,7 @@ entity fmc_masterFIP_core is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
port
(-- Clock and reset
clk_i : in std_logic; -- only one clk domain
......@@ -263,7 +263,6 @@ architecture rtl of fmc_masterFIP_core is
signal onewire_read_p, pps_is_zero : std_logic;
signal pps_load_p : std_logic;
-- chipscope
-- component chipscope_ila
-- port (
......
rtl/free_counter.vhd deleted 100644 → 0
View file @ 100564c7
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- free_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File free_counter.vhd |
-- |
-- Description Free running counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signal available. |
-- "Counting done" signal asserted simultaneous to "current count value = 0". |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for free_counter
--=================================================================================================
entity free_counter is
generic
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signals from any unit
counter_en_i : in std_logic; -- enables counting
counter_top_i : in std_logic_vector(width-1 downto 0); -- start value;
-- when zero is reached counter reloads
-- start value and restarts counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic); -- empty counter indication
end free_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of free_counter is
constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
signal counter : unsigned(width-1 downto 0):=(others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
decr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
counter_is_zero_o <= '0';
counter <= unsigned(counter_top_i) - "1";
elsif counter = zeroes then
counter_is_zero_o <= '0';
counter <= unsigned(counter_top_i) - "1";
elsif counter_en_i = '1' then
if counter = zeroes + "1" then
counter_is_zero_o <= '1';
counter <= counter - "1";
else
counter_is_zero_o <= '0';
counter <= counter - "1";
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(counter);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
rtl/irq_generator.vhd deleted 100644 → 0
View file @ 100564c7
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- irq_generator |
-- |
---------------------------------------------------------------------------------------------------
-- File irq_generator.vhd |
-- |
-- Description Interrupts generator: the unit generates three interrupts: |
-- |
-- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of |
-- timestamps written in the circular_buffer, since the last interrupt or since |
-- the startup of the acquisition, exceeds the GN4124/VME settable threshold |
-- irq_tstamp_threshold. |
-- |
-- o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
-- written in the circular_buffer (>=1 timestamp) and the amount of time passed |
-- since the last interrupt or since the acquisition startup, exceeds the |
-- GN4124/VME settable threshold irq_time_threshold. The threshold is in ms. |
-- |
-- o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
-- full (according to ACAM configuration register 11) |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 08/2013 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2012 v0.1 EG First version |
-- 04/2013 v0.2 EG line 170 added "irq_time_threshold_i > 0"; if the user doesn t want the |
-- time interrupts he sets the irq_time_threshold reg to zero; same goes |
-- for number-of-tstamps interrupts, users sets to zero to disable them |
-- 08/2013 v1 EG time irq concept in milliseconds rather than seconds |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for irq_generator
--=================================================================================================
entity irq_generator is
generic
(g_width : integer := 32);
port
-- INPUTS
-- Signal from the clks_rsts_manager
(clk_i : in std_logic; -- 125 MHz clk
rst_i : in std_logic; -- global reset
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
-- Signal from the acam_timecontrol_interface
acam_errflag_r_edge_p_i : in std_logic; -- ACAM ErrFlag rising edge; through the ACAM config reg 11
-- the ERRflag is configured to follow the full flags of the
-- Hit FIFOs; this would translate to data loss
-- Signal from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- activates tstamps acquisition from ACAM
deactivate_acq_p_i : in std_logic; -- deactivates tstamps acquisition
-- Signals from the data_formatting unit
tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
-- OUTPUTS
-- Signals to the wb_irq_controller
irq_tstamp_p_o : out std_logic; -- active if amount of tstamps > tstamps_threshold
irq_time_p_o : out std_logic; -- active if amount of tstamps < tstamps_threshold but time > time_threshold
irq_acam_err_p_o : out std_logic); -- active if ACAM err_flag_i is active
end irq_generator;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of irq_generator is
constant ZERO : std_logic_vector (8 downto 0):= "000000000";
type t_irq_st is (IDLE, TSTAMP_AND_TIME_COUNTING, RAISE_IRQ_TSTAMP, RAISE_IRQ_TIME);
signal irq_st, nxt_irq_st : t_irq_st;
signal tstamps_c_rst, time_c_rst : std_logic;
signal tstamps_c_en, time_c_en : std_logic;
signal tstamps_c_incr_en, time_c_incr_en : std_logic;
signal tstamps_c : std_logic_vector(8 downto 0);
signal time_c : std_logic_vector(g_width-1 downto 0);
signal one_ms_passed_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- INTERRUPTS GENERATOR FSM --
---------------------------------------------------------------------------------------------------
IRQ_generator_seq: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
irq_st <= IDLE;
else
irq_st <= nxt_irq_st;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
IRQ_generator_comb: process (irq_st, activate_acq_p_i, deactivate_acq_p_i, tstamps_c,
irq_tstamp_threshold_i, irq_time_threshold_i, time_c)
begin
case irq_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when IDLE =>
-----------------------------------------------
irq_tstamp_p_o <= '0';
irq_time_p_o <= '0';
tstamps_c_rst <= '1';
time_c_rst <= '1';
tstamps_c_en <= '0';
time_c_en <= '0';
-----------------------------------------------
if activate_acq_p_i = '1' then
nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
else
nxt_irq_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when TSTAMP_AND_TIME_COUNTING =>
-----------------------------------------------
irq_tstamp_p_o <= '0';
irq_time_p_o <= '0';
tstamps_c_rst <= '0';
time_c_rst <= '0';
tstamps_c_en <= '1';
time_c_en <= '1';
-----------------------------------------------
if deactivate_acq_p_i = '1' then
nxt_irq_st <= IDLE;
elsif tstamps_c > ZERO and tstamps_c >= irq_tstamp_threshold_i(8 downto 0) then -- not >= ZERO!!
nxt_irq_st <= RAISE_IRQ_TSTAMP;
elsif unsigned(irq_time_threshold_i) > 0 and time_c >= irq_time_threshold_i and tstamps_c > ZERO then
nxt_irq_st <= RAISE_IRQ_TIME;
else
nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RAISE_IRQ_TSTAMP =>
-----------------------------------------------
irq_tstamp_p_o <= '1';
irq_time_p_o <= '0';
tstamps_c_rst <= '1';
time_c_rst <= '1';
tstamps_c_en <= '0';
time_c_en <= '0';
-----------------------------------------------
if deactivate_acq_p_i = '1' then
nxt_irq_st <= IDLE;
else
nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RAISE_IRQ_TIME =>
-----------------------------------------------
irq_tstamp_p_o <= '0';
irq_time_p_o <= '1';
tstamps_c_rst <= '1';
time_c_rst <= '1';
tstamps_c_en <= '0';
time_c_en <= '0';
-----------------------------------------------
if deactivate_acq_p_i = '1' then
nxt_irq_st <= IDLE;
else
nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
-----------------------------------------------
irq_tstamp_p_o <= '0';
irq_time_p_o <= '0';
tstamps_c_rst <= '1';
time_c_rst <= '1';
tstamps_c_en <= '0';
time_c_en <= '0';
-----------------------------------------------
nxt_irq_st <= IDLE;
end case;
end process;
---------------------------------------------------------------------------------------------------
-- TIMESTAMPS COUNTER --
---------------------------------------------------------------------------------------------------
-- Incremental counter counting the amount of timestamps written since the last interrupt or the
-- last reset. The counter counts up to 255.
tstamps_counter: incr_counter
generic map
(width => 9) -- 9 digits, counting up to 255
port map
(clk_i => clk_i,
rst_i => tstamps_c_rst,
counter_top_i => "100000000",
counter_incr_en_i => tstamps_c_incr_en,
counter_is_full_o => open,
-------------------------------------------
counter_o => tstamps_c);
-------------------------------------------
tstamps_c_incr_en <= tstamps_c_en and tstamp_wr_p_i;
---------------------------------------------------------------------------------------------------
-- TIME COUNTER --
---------------------------------------------------------------------------------------------------
-- Incremental counter counting the time in milliseconds since the last interrupt or the last reset.
time_counter: incr_counter
generic map
(width => g_width)
port map
(clk_i => clk_i,
rst_i => time_c_rst,
counter_top_i => x"FFFFFFFF",
counter_incr_en_i => time_c_incr_en,
counter_is_full_o => open,
-------------------------------------------
counter_o => time_c);
-------------------------------------------
time_c_incr_en <= time_c_en and one_ms_passed_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
millisec_counter: free_counter
generic map
(width => g_width)
port map
(clk_i => clk_i,
rst_i => rst_i,
counter_en_i => '1',
counter_top_i => x"0001E848", -- 125'000 clk_i cycles = 1 ms
-------------------------------------------
counter_is_zero_o => one_ms_passed_p,
counter_o => open);
-------------------------------------------
---------------------------------------------------------------------------------------------------
-- ACAM ErrFlag IRQ --
---------------------------------------------------------------------------------------------------
irq_acam_err_p_o <= acam_errflag_r_edge_p_i;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
rtl/masterfip_rx.vhd
View file @ a030d4f6
......@@ -278,7 +278,7 @@ begin
rx_ctrl_byte_o <= (others => '0');
else
if rx_byte_ready_p = '1' then
if unsigned(rx_byte_index) = resize(unsigned(c_CTRL_BYTE_INDEX),9) then
if unsigned(rx_byte_index) = resize(unsigned(c_CTRL_BYTE_INDEX),C_FRAME_BYTES_CNT_LGTH) then
rx_ctrl_byte_o <= rx_byte;
else
byte0 <= rx_byte;
......
syn/spec/spec_masterfip_mt.par
View file @ a030d4f6
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Apr 12 12:39:20 2017
PCBE13457:: Thu Apr 20 22:28:26 2017
par -w -intstyle ise -ol high -mt off spec_masterfip_mt_map.ncd
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -20,7 +20,7 @@ WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 18 days after which you will not qualify
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 10 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
......@@ -36,15 +36,15 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,635 out of 54,576 23%
Number used as Flip Flops: 12,633
Number of Slice Registers: 12,622 out of 54,576 23%
Number used as Flip Flops: 12,620
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,741 out of 27,288 57%
Number used as logic: 12,500 out of 27,288 45%
Number using O6 output only: 10,376
Number using O5 output only: 393
Number of Slice LUTs: 15,763 out of 27,288 57%
Number used as logic: 12,382 out of 27,288 45%
Number using O6 output only: 10,259
Number using O5 output only: 392
Number using O5 and O6: 1,731
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
......@@ -54,18 +54,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 413
Number with same-slice register load: 384
Number used exclusively as route-thrus: 553
Number with same-slice register load: 524
Number with same-slice carry load: 29
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,480 out of 6,822 80%
Number of occupied Slices: 5,213 out of 6,822 76%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 19,263
Number with an unused Flip Flop: 7,657 out of 19,263 39%
Number with an unused LUT: 3,522 out of 19,263 18%
Number of fully used LUT-FF pairs: 8,084 out of 19,263 41%
Number of LUT Flip Flop pairs used: 18,849
Number with an unused Flip Flop: 7,405 out of 18,849 39%
Number with an unused LUT: 3,086 out of 18,849 16%
Number of fully used LUT-FF pairs: 8,358 out of 18,849 44%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -136,158 +136,156 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 111354 unrouted; REAL time: 20 secs
Phase 1 : 110609 unrouted; REAL time: 20 secs
Phase 2 : 102665 unrouted; REAL time: 23 secs
Phase 2 : 101920 unrouted; REAL time: 23 secs
Phase 3 : 52819 unrouted; REAL time: 1 mins 5 secs
Phase 3 : 51722 unrouted; REAL time: 1 mins 2 secs
Phase 4 : 55464 unrouted; (Setup:2990, Hold:8015, Component Switching Limit:0) REAL time: 1 mins 35 secs
Phase 4 : 52377 unrouted; (Setup:0, Hold:8043, Component Switching Limit:0) REAL time: 1 mins 12 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:8376, Hold:7012, Component Switching Limit:0) REAL time: 10 mins 39 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 6 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 17 mins 53 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 18 mins 53 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 8 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 18 mins 53 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 9 : 0 unrouted; (Setup:3516, Hold:0, Component Switching Limit:0) REAL time: 18 mins 55 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 25 secs
Phase 10 : 0 unrouted; (Setup:2991, Hold:0, Component Switching Limit:0) REAL time: 19 mins
Total REAL time to Router completion: 19 mins
Total CPU time to Router completion: 19 mins 18 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 30 secs
Total REAL time to Router completion: 5 mins 30 secs
Total CPU time to Router completion: 5 mins 39 secs
Partition Implementation Status
-------------------------------
......@@ -306,7 +304,7 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4429 | 0.548 | 1.759 |
| sys | BUFGMUX_X2Y3| No | 4364 | 0.548 | 1.759 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
......@@ -325,23 +323,7 @@ the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 2991 (Setup: 2991, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 6
......@@ -352,13 +334,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | -0.622ns| 10.622ns| 17| 2991
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.278ns| | 0| 0
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.034ns| 9.966ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.277ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.064ns| 4.936ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.086ns| | 0| 0
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.092ns| 4.908ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.037ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
......@@ -419,8 +401,8 @@ Derived Constraints for TS_clk_125m_pllref_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 8.498ns| 0| 17| 0| 4836561|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 10.622ns| N/A| 17| 0| 4836561| 0|
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.973ns| 0| 0| 0| 4834021|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.966ns| N/A| 0| 0| 4834021| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -430,20 +412,20 @@ Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.936ns| 0| 0| 0| 4827|
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.908ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.936ns| 0| 0| 0| 4827|
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.908ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.936ns| N/A| 0| 0| 4827| 0|
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.908ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
......@@ -457,17 +439,17 @@ All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 19 mins 7 secs
Total CPU time to PAR completion: 19 mins 24 secs
Total REAL time to PAR completion: 5 mins 37 secs
Total CPU time to PAR completion: 5 mins 45 secs
Peak Memory Usage: 939 MB
Peak Memory Usage: 886 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 17 errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 74
Number of warning messages: 73
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
......
syn/spec/spec_masterfip_mt.syr
View file @ a030d4f6
......@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.07 secs
Total CPU time to Xst completion: 0.06 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.07 secs
Total CPU time to Xst completion: 0.06 secs
--> Reading design: spec_masterfip_mt.prj
......@@ -978,6 +978,8 @@ WARNING:HDLCompiler:634 - "C:\masterFIP\fresh\masterfip-gw\ip_cores\wr-node-core
Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
Note: "Mapping slave #0[0x0/0x0]"
WARNING:HDLCompiler:244 - "C:\masterFIP\fresh\masterfip-gw\rtl\masterFIP_pkg.vhd" Line 118: Binding entity fmc_masterfip_core does not have generic values_for_simul
INFO:HDLCompiler:1408 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" Line 166. fmc_masterfip_core is declared here
Elaborating entity <fmc_masterFIP_core> (architecture <rtl>) with generics from library <work>.
......@@ -1033,6 +1035,7 @@ INFO:HDLCompiler:679 - "C:\masterFIP\fresh\masterfip-gw\ip_cores\general-cores\m
WARNING:HDLCompiler:1127 - "C:\masterFIP\fresh\masterfip-gw\ip_cores\general-cores\modules\common\gc_ds182x_interface.vhd" Line 385: Assignment to end_p ignored, since the identifier is never used
Elaborating entity <wf_decr_counter> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:1408 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" Line 166. fmc_masterfip_core is declared here
=========================================================================
* HDL Synthesis *
......@@ -3883,32 +3886,32 @@ Synthesizing Unit <fmc_masterFIP_core>.
Related source file is "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd".
g_span = 32
g_width = 32
values_for_simul = false
g_simul = false
WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_adr_i<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 350: Output port <npulse_o> of the instance <cmp_ext_sync_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 350: Output port <ppulse_o> of the instance <cmp_ext_sync_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 370: Output port <synced_o> of the instance <cmp_ext_sync_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 370: Output port <npulse_o> of the instance <cmp_ext_sync_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 379: Output port <counter_is_full_o> of the instance <cmp_ext_sync_p_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 447: Output port <counter_is_zero_o> of the instance <cmp_turnaround_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 469: Output port <counter_is_zero_o> of the instance <cmp_silence_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 487: Output port <rx_byte_o> of the instance <cmp_masterfip_rx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 487: Output port <rx_byte_ready_p_o> of the instance <cmp_masterfip_rx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 562: Output port <counter_is_full_o> of the instance <cmp_rx_crc_err_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 634: Output port <npulse_o> of the instance <cmp_fd_wdgn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 634: Output port <ppulse_o> of the instance <cmp_fd_wdgn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 657: Output port <synced_o> of the instance <cmp_fd_wdgn_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 657: Output port <npulse_o> of the instance <cmp_fd_wdgn_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 687: Output port <npulse_o> of the instance <cmp_fd_rxcdn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 687: Output port <ppulse_o> of the instance <cmp_fd_rxcdn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 718: Output port <npulse_o> of the instance <cmp_fd_txer_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 718: Output port <ppulse_o> of the instance <cmp_fd_txer_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 739: Output port <synced_o> of the instance <cmp_fd_txer_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 739: Output port <npulse_o> of the instance <cmp_fd_txer_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 748: Output port <counter_is_full_o> of the instance <cmp_fd_txer_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 786: Output port <id_ok_o> of the instance <cmp_onewire> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 799: Output port <counter_o> of the instance <cmp_pps_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 349: Output port <npulse_o> of the instance <cmp_ext_sync_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 349: Output port <ppulse_o> of the instance <cmp_ext_sync_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 369: Output port <synced_o> of the instance <cmp_ext_sync_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 369: Output port <npulse_o> of the instance <cmp_ext_sync_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 378: Output port <counter_is_full_o> of the instance <cmp_ext_sync_p_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 446: Output port <counter_is_zero_o> of the instance <cmp_turnaround_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 468: Output port <counter_is_zero_o> of the instance <cmp_silence_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 486: Output port <rx_byte_o> of the instance <cmp_masterfip_rx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 486: Output port <rx_byte_ready_p_o> of the instance <cmp_masterfip_rx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 561: Output port <counter_is_full_o> of the instance <cmp_rx_crc_err_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 633: Output port <npulse_o> of the instance <cmp_fd_wdgn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 633: Output port <ppulse_o> of the instance <cmp_fd_wdgn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 656: Output port <synced_o> of the instance <cmp_fd_wdgn_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 656: Output port <npulse_o> of the instance <cmp_fd_wdgn_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 686: Output port <npulse_o> of the instance <cmp_fd_rxcdn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 686: Output port <ppulse_o> of the instance <cmp_fd_rxcdn_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 717: Output port <npulse_o> of the instance <cmp_fd_txer_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 717: Output port <ppulse_o> of the instance <cmp_fd_txer_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 738: Output port <synced_o> of the instance <cmp_fd_txer_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 738: Output port <npulse_o> of the instance <cmp_fd_txer_deglitch_p_detect> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 747: Output port <counter_is_full_o> of the instance <cmp_fd_txer_cnt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 785: Output port <id_ok_o> of the instance <cmp_onewire> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" line 798: Output port <counter_o> of the instance <cmp_pps_gen> is unconnected or connected to loadless signal.
Found 9-bit register for signal <reg_to_mt_rx_stat_bytes_num_i>.
Found 1-bit register for signal <reg_to_mt_rx_stat_pream_ok_i>.
Found 1-bit register for signal <reg_to_mt_rx_stat_frame_crc_err_i>.
......@@ -3919,7 +3922,7 @@ INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\rtl\fmc_masterFIP_core.vhd" lin
Found 32-bit register for signal <reg_to_mt_ds1820_id_lsb_i>.
Found 32-bit register for signal <reg_to_mt_ds1820_id_msb_i>.
Found 1-bit register for signal <reg_to_mt_rx_stat_frame_ok_i>.
Found 9-bit subtractor for signal <GND_865_o_GND_865_o_sub_5_OUT<8:0>> created at line 524.
Found 9-bit subtractor for signal <GND_865_o_GND_865_o_sub_5_OUT<8:0>> created at line 523.
Found 4x12-bit Read Only RAM for signal <extend>
Summary:
inferred 1 RAM(s).
......@@ -9895,14 +9898,14 @@ cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_p2l_dma_master/cmp_to_wb_fifo/
=========================================================================
Total REAL time to Xst completion: 184.00 secs
Total CPU time to Xst completion: 184.96 secs
Total REAL time to Xst completion: 173.00 secs
Total CPU time to Xst completion: 173.48 secs
-->
Total memory usage is 631784 kilobytes
Total memory usage is 633064 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3946 ( 0 filtered)
Number of warnings : 3947 ( 0 filtered)
Number of infos : 535 ( 0 filtered)
syn/spec/spec_masterfip_mt.twr
View file @ a030d4f6
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.xise
View file @ a030d4f6
......@@ -102,7 +102,7 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
......@@ -228,7 +228,7 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_masterfip_mt_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_masterfip_mt_timesim.v" xil_pn:valueState="default"/>
......@@ -241,6 +241,7 @@
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -306,7 +307,7 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
......@@ -414,10 +415,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
syn/spec/spec_masterfip_mt_map.mrp
View file @ a030d4f6
This source diff could not be displayed because it is too large. You can view the blob instead.
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