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MasterFIP - Gateware
Commit 8a4e7097 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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sim not dependent on proasic3

parent f667cd35
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Showing with 85 additions and 256 deletions
sim/spec/tb_masterfip.do
View file @ 8a4e7097
......@@ -21,8 +21,8 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
......@@ -79,7 +79,7 @@ vlog "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/l
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd"
......@@ -131,11 +131,9 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_s
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vlib proasic3
vcom -explicit -93 "../../../../../Microsemi/Libero_v11.4/Designer/lib/vtl/95/proasic3.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_package.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_incr_counter.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_decr_counter.vhd"
......@@ -167,10 +165,10 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_pr
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_crc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_incr_counter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_decr_counter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_crc.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/util.vhd"
vcom -explicit -93 "../../rtl/masterFIP_pkg.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_tx_serializer.vhd"
......@@ -198,17 +196,17 @@ vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_co
vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_tx_serializer.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_tx_osc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_status_bytes_gen.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_osc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_deserializer.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_deglitcher.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_permit.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_data_lgth_calc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_bytes_retriever.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_cons_outcome.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_csr.vhd"
......@@ -231,27 +229,28 @@ vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_config.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_wb_controller.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_reset_unit.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_production.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_model_constr_decoder.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_jtag_controller.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_fd_transmitter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_fd_receiver.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_engine_control.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_consumption.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/mem_model.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd"
vcom -explicit -93 "../../top/spec/spec_masterfip_mt.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/nanofip.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/nanofip.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router.vhd"
vcom -explicit -93 "../../sim/spec/testbench/board_settings.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_masterFIP.vhd"
vlog "C:/EDA/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
vlog $env(XILINX)/verilog/src/glbl.v
#
# Call vsim to invoke simulator
#
......
sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd
View file @ 8a4e7097
......@@ -12,21 +12,13 @@
---------------------------------------------------------------------------------------------------
-- File dualram_512x8.vhd |
-- |
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with |
-- Description A simulation model of the nanoFIP dualram_512x8 module without dependency on the |
-- PROASIC3 library. |
-- o word width: 8 bits and |
-- o depth : 512 bytes. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/12/2010 |
-- Version v0.02 |
-- Depends on ProASIC3 lib |
---------------- |
-- Last changes |
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the |
-- address is given (otherwise it was 2 clock cycles later) slack |
-- checked and is ok! code cleaned-up and commented |
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up |
-- Authors Tomasz Wlostowski (Tomasz.Wlostowski@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -50,11 +42,9 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Component specific library
library PROASIC3; -- ProASIC3 library
use PROASIC3.all;
--=================================================================================================
......@@ -63,28 +53,28 @@ use PROASIC3.all;
entity dualram_512x8 is port(
-- INPUTS
-- Inputs concerning port A
CLKA : in std_logic; -- clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); -- address A
DINA : in std_logic_vector (7 downto 0); -- data in A
RWA : in std_logic; -- read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port A
CLKA : in std_logic; -- clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); -- address A
DINA : in std_logic_vector (7 downto 0); -- data in A
RWA : in std_logic; -- read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port B
CLKB : in std_logic; -- clock B for synchronous read/ write operations
ADDRB : in std_logic_vector (8 downto 0); -- address B
DINB : in std_logic_vector (7 downto 0); -- data in B
RWB : in std_logic; -- read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port B
CLKB : in std_logic; -- clock B for synchronous read/ write operations
ADDRB : in std_logic_vector (8 downto 0); -- address B
DINB : in std_logic_vector (7 downto 0); -- data in B
RWB : in std_logic; -- read/ write mode; 1 for reading, 0 for writing
-- Reset
RESETn : in std_logic; -- sets all outputs low; does not reset the memory
-- Reset
RESETn : in std_logic; -- sets all outputs low; does not reset the memory
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); -- data out A
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); -- data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0));-- data out B
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0)); -- data out B
end dualram_512x8;
......@@ -93,195 +83,34 @@ end dualram_512x8;
--=================================================================================================
architecture RAM4K9 of dualram_512x8 is
---------------------------------------------------------------------------------------------------
-- General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
-- pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9.
-- Both ports are capable of reading and writing, making it possible to write with both ports or
-- read with both ports simultaneously. Moreover, reading from one port while writing to the other
-- is possible.
-- WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1:
-- Aspect ratio configuration.
-- WENA, WENB:
-- Switching between Read and Write modes for the respective ports.
-- A Low indicates Write operation and a High indicates a Read.
-- BLKA, BLKB:
-- Active low enable for the respective ports.
-- PIPEA, PIPEB:
-- Control of the optional pipeline stages.
-- A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output
-- in the same clock cycle.
-- A High indicates a pipelined Read and data appears on the output in the next clock cycle.
-- WMODEA, WMODEB:
-- Configuration of the behavior of the output when the RAM is in the Write mode.
-- A Low on this signal makes the output retain data from the previous Read. A High indicates a
-- pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0,
ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6,
ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0,
DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0,
DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0,
WIDTHA0, WIDTHA1,
WIDTHB0, WIDTHB1,
PIPEA, PIPEB,
WMODEA, WMODEB,
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
----------------------------------------------------
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
----------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component VCC
component VCC
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component GND
component GND
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
signal POWER, GROUND : std_logic;
type t_ram_array is array(0 to 511) of std_logic_vector(7 downto 0);
shared variable ram : t_ram_array;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
-- The following configuration has been applied:
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
-- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND)
-- o BLKA, BLKB : GND (ports enabled)
-- o PIPEA, PIPEB : GND (not pipelined read)
-- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
DINA5 => DINA(5),
DINA4 => DINA(4),
DINA3 => DINA(3),
DINA2 => DINA(2),
DINA1 => DINA(1),
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
ADDRA1 => ADDRA(1),
ADDRA0 => ADDRA(0),
-- read/ write mode for A
WENA => RWA,
-- clock for A
CLKA => CLKA,
-- aspect ratio, block, pipeline, write mode configurations for port A
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,
WMODEA => GROUND,
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
DINB5 => DINB(5),
DINB4 => DINB(4),
DINB3 => DINB(3),
DINB2 => DINB(2),
DINB1 => DINB(1),
DINB0 => DINB(0),
-- address B (512 bytes depth, (8 downto 0))
ADDRB11 => GROUND,
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- input reset
RESET => RESETn,
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0));
-------------------------------
process(CLKA)
begin
if rising_edge(CLKA) then
if(RWA = '0') then
ram(to_integer(unsigned(ADDRA) mod 512)) := DINA;
else
DOUTA <= ram(to_integer(unsigned(ADDRA) mod 512));
end if;
end if;
end process;
process(CLKB)
begin
if rising_edge(CLKB) then
if(RWB = '0') then
ram(to_integer(unsigned(ADDRB) mod 512)) := DINB;
else
DOUTB <= ram(to_integer(unsigned(ADDRB) mod 512));
end if;
end if;
end process;
end RAM4K9;
--=================================================================================================
......
syn/spec/spec_masterfip_mt.xise
View file @ 8a4e7097
......@@ -68,6 +68,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="../../sim/spec/tb_masterfip.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
......@@ -276,8 +277,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_masterfip_mt" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -300,7 +301,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_masterfip_mt" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -317,10 +318,10 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
......
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