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MasterFIP - Gateware
Commit 76584c13 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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changed to gitlab mockturtle submodule

parent ded41436
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.gitmodules
View file @ 76584c13
......@@ -13,3 +13,6 @@
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "ip_cores/mockturtle"]
path = ip_cores/mockturtle
url = https://gitlab.cern.ch/coht/mockturtle.git
mockturtle @ bb80c5b3
Subproject commit bb80c5b3009265db7d3fc595d859350a68cdf881
syn/spec/spec_masterfip_mt.par
View file @ 76584c13
Release 14.7 par P.20131013 (nt64)
Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Jul 26 12:07:41 2017
PCBE13457:: Thu Jan 17 18:18:19 2019
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\14.7\ISE_DS\ISE\.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
......@@ -108,10 +108,10 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -122,65 +122,65 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
......@@ -189,25 +189,25 @@ Phase 1 : 110289 unrouted; REAL time: 20 secs
Phase 2 : 101662 unrouted; REAL time: 23 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 7 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 12 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 23 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 29 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 43 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 49 secs
Total REAL time to Router completion: 7 mins 49 secs
Total CPU time to Router completion: 7 mins 58 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 47 secs
Total REAL time to Router completion: 8 mins 47 secs
Total CPU time to Router completion: 8 mins 55 secs
Partition Implementation Status
-------------------------------
......@@ -367,10 +367,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 7 mins 56 secs
Total CPU time to PAR completion: 8 mins 5 secs
Total REAL time to PAR completion: 8 mins 55 secs
Total CPU time to PAR completion: 9 mins 3 secs
Peak Memory Usage: 889 MB
Peak Memory Usage: 666 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt.syr
View file @ 76584c13
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syn/spec/spec_masterfip_mt.twr
View file @ 76584c13
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.xise
View file @ 76584c13
......@@ -48,7 +48,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -382,13 +382,13 @@
</libraries>
<files>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
......@@ -396,7 +396,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../rtl/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
......@@ -404,23 +404,23 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_etherbone_output.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/mqueue/wrn_mqueue_etherbone_output.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
......@@ -458,33 +458,33 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="182"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/mockturtle/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="180"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
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......@@ -1088,35 +1084,35 @@
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......@@ -1124,119 +1120,119 @@
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......@@ -1244,23 +1240,23 @@
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......@@ -1268,23 +1264,23 @@
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......@@ -1411,6 +1407,10 @@
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......
syn/spec/spec_masterfip_mt_map.mrp
View file @ 76584c13
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