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MasterFIP - Gateware
Commits
6921cd9e
Commit
6921cd9e
authored
Dec 03, 2015
by
Evangelia Gousiou
Browse files
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added the control of the relays that connect/disconnect the adc
parent
e1f798ee
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9 changed files
with
167 additions
and
76 deletions
+167
-76
fmc_masterFIP_core.vhd
rtl/fmc_masterFIP_core.vhd
+4
-0
fmc_masterfip_csr.vhd
rtl/fmc_masterfip_csr.vhd
+21
-7
masterFIP_pkg.vhd
rtl/masterFIP_pkg.vhd
+4
-0
fmc_masterfip_csr.wb
rtl/wbgen/fmc_masterfip_csr.wb
+24
-2
spec_masterFIP.xise
syn/spec/spec_masterFIP.xise
+74
-43
spec_masterFIP.ucf
top/spec/spec_masterFIP.ucf
+7
-0
spec_masterFIP.vhd
top/spec/spec_masterFIP.vhd
+4
-0
spec_top.ucf
top/spec_wrnode/spec_top.ucf
+4
-3
spec_top.vhd
top/spec_wrnode/spec_top.vhd
+25
-21
No files found.
rtl/fmc_masterFIP_core.vhd
View file @
6921cd9e
...
...
@@ -82,6 +82,8 @@ entity fmc_masterFIP_core is
adc_1v8_shdn_n_o
:
out
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
adc_prim_conn_n_o
:
out
std_logic
;
adc_sec_conn_n_o
:
out
std_logic
;
-- FielDrive
fd_rxcdn_i
:
in
std_logic
;
...
...
@@ -203,6 +205,8 @@ begin
mf_adc_1v8_shdn_n_o
=>
adc_1v8_shdn_n_o
,
mf_adc_m5v_shdn_n_o
=>
adc_m5v_shdn_n_o
,
mf_adc_5v_en_n_o
=>
adc_5v_en_n_o
,
mf_adc_prim_conn_n_o
=>
adc_prim_conn_n_o
,
mf_adc_sec_conn_n_o
=>
adc_sec_conn_n_o
,
-- external sync pulse
mf_ext_sync_term_en_o
=>
ext_sync_term_en_o
,
mf_ext_sync_dir_o
=>
ext_sync_dir_o
,
...
...
rtl/fmc_masterfip_csr.vhd
View file @
6921cd9e
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 1
0/27/15 14:50:0
0
-- Created : 1
1/17/15 15:00:5
0
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
...
...
@@ -34,12 +34,16 @@ entity fmc_masterfip_csr is
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rstn'
mf_rstn_lock_o
:
out
std_logic_vector
(
15
downto
0
);
mf_rstn_lock_wr_o
:
out
std_logic
;
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc
power supplies
'
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc'
mf_adc_1v8_shdn_n_o
:
out
std_logic
;
-- Port for BIT field: 'm5v_shdn_n' in reg: 'adc
power supplies
'
-- Port for BIT field: 'm5v_shdn_n' in reg: 'adc'
mf_adc_m5v_shdn_n_o
:
out
std_logic
;
-- Port for BIT field: '5v_en_n' in reg: 'adc
power supplies
'
-- Port for BIT field: '5v_en_n' in reg: 'adc'
mf_adc_5v_en_n_o
:
out
std_logic
;
-- Port for BIT field: 'prim_conn_n' in reg: 'adc'
mf_adc_prim_conn_n_o
:
out
std_logic
;
-- Port for BIT field: 'sec_conn_n' in reg: 'adc'
mf_adc_sec_conn_n_o
:
out
std_logic
;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
mf_ext_sync_term_en_o
:
out
std_logic
;
-- Port for BIT field: 'tranceiver direction' in reg: 'ext sync'
...
...
@@ -52,7 +56,7 @@ entity fmc_masterfip_csr is
mf_ext_sync_p_cnt_rst_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
mf_ext_sync_p_cnt_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: '150ohms terination of the bus' in reg: '
150ohms
bus termination'
-- Port for BIT field: '150ohms terination of the bus' in reg: 'bus termination'
mf_bus_term_en_n_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'speed' in reg: 'speed'
mf_speed_i
:
in
std_logic_vector
(
1
downto
0
);
...
...
@@ -380,6 +384,8 @@ signal mf_rstn_fd_int : std_logic ;
signal
mf_adc_1v8_shdn_n_int
:
std_logic
;
signal
mf_adc_m5v_shdn_n_int
:
std_logic
;
signal
mf_adc_5v_en_n_int
:
std_logic
;
signal
mf_adc_prim_conn_n_int
:
std_logic
;
signal
mf_adc_sec_conn_n_int
:
std_logic
;
signal
mf_ext_sync_term_en_int
:
std_logic
;
signal
mf_ext_sync_dir_int
:
std_logic
;
signal
mf_ext_sync_oe_int
:
std_logic
;
...
...
@@ -496,6 +502,8 @@ begin
mf_adc_1v8_shdn_n_int
<=
'0'
;
mf_adc_m5v_shdn_n_int
<=
'0'
;
mf_adc_5v_en_n_int
<=
'0'
;
mf_adc_prim_conn_n_int
<=
'0'
;
mf_adc_sec_conn_n_int
<=
'0'
;
mf_ext_sync_term_en_int
<=
'0'
;
mf_ext_sync_dir_int
<=
'0'
;
mf_ext_sync_oe_int
<=
'0'
;
...
...
@@ -644,17 +652,19 @@ begin
mf_adc_1v8_shdn_n_int
<=
wrdata_reg
(
0
);
mf_adc_m5v_shdn_n_int
<=
wrdata_reg
(
1
);
mf_adc_5v_en_n_int
<=
wrdata_reg
(
2
);
mf_adc_prim_conn_n_int
<=
wrdata_reg
(
8
);
mf_adc_sec_conn_n_int
<=
wrdata_reg
(
9
);
end
if
;
rddata_reg
(
0
)
<=
mf_adc_1v8_shdn_n_int
;
rddata_reg
(
1
)
<=
mf_adc_m5v_shdn_n_int
;
rddata_reg
(
2
)
<=
mf_adc_5v_en_n_int
;
rddata_reg
(
8
)
<=
mf_adc_prim_conn_n_int
;
rddata_reg
(
9
)
<=
mf_adc_sec_conn_n_int
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
...
...
@@ -1957,6 +1967,10 @@ begin
mf_adc_m5v_shdn_n_o
<=
mf_adc_m5v_shdn_n_int
;
-- 5v_en_n
mf_adc_5v_en_n_o
<=
mf_adc_5v_en_n_int
;
-- prim_conn_n
mf_adc_prim_conn_n_o
<=
mf_adc_prim_conn_n_int
;
-- sec_conn_n
mf_adc_sec_conn_n_o
<=
mf_adc_sec_conn_n_int
;
-- termination enable
mf_ext_sync_term_en_o
<=
mf_ext_sync_term_en_int
;
-- tranceiver direction
...
...
rtl/masterFIP_pkg.vhd
View file @
6921cd9e
...
...
@@ -191,6 +191,8 @@ package masterFIP_pkg is
mf_adc_1v8_shdn_n_o
:
out
std_logic
;
mf_adc_m5v_shdn_n_o
:
out
std_logic
;
mf_adc_5v_en_n_o
:
out
std_logic
;
mf_adc_prim_conn_n_o
:
out
std_logic
;
mf_adc_sec_conn_n_o
:
out
std_logic
;
mf_ext_sync_term_en_o
:
out
std_logic
;
mf_ext_sync_dir_o
:
out
std_logic
;
...
...
@@ -394,6 +396,8 @@ package masterFIP_pkg is
adc_1v8_shdn_n_o
:
out
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
adc_prim_conn_n_o
:
out
std_logic
;
adc_sec_conn_n_o
:
out
std_logic
;
aux_o
:
out
std_logic_vector
(
7
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
...
...
rtl/wbgen/fmc_masterfip_csr.wb
View file @
6921cd9e
...
...
@@ -67,7 +67,7 @@ peripheral {
-- ADC power supplies --
-------------------------------------------------------------------------------
reg {
name = "adc
power supplies
";
name = "adc";
prefix = "adc";
field {
...
...
@@ -99,6 +99,28 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "prim_conn_n";
prefix = "prim_conn_n";
description = "write 0: enable the prim_conn_n\
write 1: disable the prim_conn_n";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "sec_conn_n";
prefix = "sec_conn_n";
description = "write 0: enable the sec_conn_n\
write 1: disable the sec_conn_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
...
...
@@ -177,7 +199,7 @@ peripheral {
-- bus termination --
-------------------------------------------------------------------------------
reg {
name = "
150ohms
bus termination";
name = "bus termination";
prefix = "bus_term_en_n";
field {
...
...
syn/spec/spec_masterFIP.xise
View file @
6921cd9e
This diff is collapsed.
Click to expand it.
top/spec/spec_masterFIP.ucf
View file @
6921cd9e
...
...
@@ -94,6 +94,12 @@ NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_prim_conn_n_o" LOC = V7;
NET "adc_prim_conn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_sec_conn_n_o" LOC = W8;
NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
...
...
@@ -205,6 +211,7 @@ NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
...
...
top/spec/spec_masterFIP.vhd
View file @
6921cd9e
...
...
@@ -162,6 +162,8 @@ entity spec_masterFIP is
adc_1v8_shdn_n_o
:
out
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
adc_prim_conn_n_o
:
out
std_logic
;
adc_sec_conn_n_o
:
out
std_logic
;
-- FielDrive
fd_rxcdn_i
:
in
std_logic
;
...
...
@@ -466,6 +468,8 @@ begin
adc_1v8_shdn_n_o
=>
adc_1v8_shdn_n_o
,
adc_m5v_shdn_n_o
=>
adc_m5v_shdn_n_o
,
adc_5v_en_n_o
=>
adc_5v_en_n_o
,
adc_prim_conn_n_o
=>
adc_prim_conn_n_o
,
adc_sec_conn_n_o
=>
adc_sec_conn_n_o
,
-- WISHBONE interface with the GN4124 core
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_MASTERFIP
)
.
adr
,
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_MASTERFIP
)
.
dat
,
...
...
top/spec_wrnode/spec_top.ucf
View file @
6921cd9e
...
...
@@ -228,10 +228,11 @@ NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_prim_conn_n_o" LOC = V7;
NET "adc_prim_conn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_sec_conn_n_o" LOC = W8;
NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
...
...
top/spec_wrnode/spec_top.vhd
View file @
6921cd9e
...
...
@@ -133,6 +133,8 @@ entity spec_top is
adc_1v8_shdn_n_o
:
out
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
adc_prim_conn_n_o
:
out
std_logic
;
adc_sec_conn_n_o
:
out
std_logic
;
-- WorldFIP LEDs
led_tx_err_n_o
:
out
std_logic
;
...
...
@@ -159,10 +161,10 @@ constant c_hmq_config : t_wrn_mqueue_config :=
(
out_slot_count
=>
4
,
out_slot_config
=>
(
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (to host)
-- was entries => 4
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (to host)
-- was entries => 4
2
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 0
-- was entries => 4
3
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 1
-- was entries => 4
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (to host)
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (to host)
2
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 0
3
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 1
others
=>
(
0
,
0
)),
in_slot_count
=>
2
,
...
...
@@ -311,6 +313,8 @@ begin
adc_1v8_shdn_n_o
=>
adc_1v8_shdn_n_o
,
adc_m5v_shdn_n_o
=>
adc_m5v_shdn_n_o
,
adc_5v_en_n_o
=>
adc_5v_en_n_o
,
adc_prim_conn_n_o
=>
adc_prim_conn_n_o
,
adc_sec_conn_n_o
=>
adc_sec_conn_n_o
,
-- WISHBONE interface with
wb_adr_i
=>
fmc_dp_wb_out
.
adr
,
wb_dat_i
=>
fmc_dp_wb_out
.
dat
,
...
...
@@ -356,26 +360,26 @@ begin
pulse_i
=>
aux
(
1
),
extended_o
=>
rx_act
);
--
clk_40m_sys_drive_led: process (clk_sys)
--
begin
--
if rising_edge(clk_sys) then
--
if(rst_n_sys = '0') then
--
led_clk_40m_aux <= "01111111";
--
led_clk_40m_divider <= (others => '0');
--
else
--
led_clk_40m_divider <= led_clk_40m_divider+ 1;
--
if(led_clk_40m_divider = 0) then
--
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
--
end if;
--
end if;
--
end if;
--
end process;
clk_40m_sys_drive_led
:
process
(
clk_sys
)
begin
if
rising_edge
(
clk_sys
)
then
if
(
rst_n_sys
=
'0'
)
then
led_clk_40m_aux
<=
"01111111"
;
led_clk_40m_divider
<=
(
others
=>
'0'
);
else
led_clk_40m_divider
<=
led_clk_40m_divider
+
1
;
if
(
led_clk_40m_divider
=
0
)
then
led_clk_40m_aux
<=
led_clk_40m_aux
(
6
downto
0
)
&
led_clk_40m_aux
(
7
);
end
if
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- --
--
led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_err_n_o
<=
led_clk_40m_aux
(
0
);
led_tx_act_n_o
<=
aux
(
3
);
led_tx_err_n_o
<=
aux
(
5
);
--
led_tx_err_n_o <= aux(5);
led_rx_err_n_o
<=
aux
(
2
);
led_rx_act_n_o
<=
aux
(
6
);
led_out_of_sync_n_o
<=
aux
(
7
);
...
...
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