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MasterFIP - Gateware
Commit 3c5faced authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- added DAC SPI for the 25MHz OSC1 of the SPEC (mainly to be able to set it to… 

- added DAC SPI for the 25MHz OSC1 of the SPEC (mainly to be able to set it to the middle range where the OSC stability is maximum)
- added corresponding reg in fmc_masterfip_csr.wb
- cleanup of testbench
parent 9aa29601
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Showing with 5858 additions and 1656 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 3c5faced
......@@ -159,27 +159,32 @@ entity fmc_masterFIP_core is
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- DAC configuration (to set OSC1 to its middle range where the stability is max)
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WISHBONE classic bus interface
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0);
-- Aux
aux_o : out std_logic_vector(7 downto 0)); -- group of 8 aux signals to pass to the higher levels
......@@ -233,8 +238,13 @@ architecture rtl of fmc_masterFIP_core is
signal fd_txer_cnt : std_logic_vector(31 downto 0);
-- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- DAC
signal dac_value : std_logic_vector(15 downto 0);
signal dac_load, dac_load_p : std_logic;
-- ext_sync
signal ext_sync, ext_sync_filt : std_logic;
signal ext_sync_tst_n : std_logic;
signal ext_sync_di : std_logic_vector(0 downto 0);
-- LEDs
signal sync_led, out_of_sync_led : std_logic;
-- debug
......@@ -304,6 +314,9 @@ begin
mf_ext_sync_tst_n_o => ext_sync_tst_n,
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- DAC configuration
mf_dac_config_value_o => dac_value,
mf_dac_config_load_o => dac_load,
-- bus speed
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
......@@ -519,16 +532,34 @@ begin
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
-- TODO: add antiglitch filter; maybe also disable the reception of a new pulse for some time after
-- the previous pulse
-- TODO: maybe also disable the reception of a new pulse for some time after the previous pulse
-- synchronizer and edge detection
-- input synchronizer
cmp_ext_sync_sync: gc_sync_register
generic map(g_width => 1)
port map
(clk_i => clk_i,
rst_n_a_i => core_rst_n,
d_i => ext_sync_di,
q_o(0) => ext_sync);
ext_sync_di(0) <= ext_sync_i; -- d_i is std_logic_vector; in our case there is only 1 bit
-- deglitch filter
cmp_ext_sync_glitch_filt: gc_glitch_filt
generic map(g_len => 10) -- glitches up to 100ns are ignored;
port map -- Note that the filter adds a 100ns delay to the ext_sync signal
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => ext_sync,
dat_o => ext_sync_filt);
-- edge detection
cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_i,
data_i => ext_sync_filt,
ppulse_o => ext_sync_p);
-- pulses counter
......@@ -551,7 +582,7 @@ begin
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
-- counter counting the macrocycle time
cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31)
......@@ -585,6 +616,8 @@ begin
counter_o => num_of_macrocyc_cnt);
num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full;
---------------------------------------------------------------------------------------------------
-- turnaround counter --
---------------------------------------------------------------------------------------------------
......@@ -818,7 +851,7 @@ begin
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_wdgn_i,
ppulse_o => fd_wdgn_p);
ppulse_o => fd_wdgn_p);
-- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle
p_fd_wdgn_capture : process(clk_i)
......@@ -844,7 +877,7 @@ begin
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_txer_i,
ppulse_o => fd_txer_p);
ppulse_o => fd_txer_p);
-- counter counting the number of fd_wdgn_p
cmp_fd_wdgn_cnt:incr_counter
......@@ -857,7 +890,7 @@ begin
counter_o => fd_txer_cnt);
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0'
else '0';
else '0';
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture : process(clk_i)
......@@ -875,9 +908,40 @@ begin
end if;
end process;
---------------------------------------------------------------------------------------------------
-- LEDs --
-- DAC --
---------------------------------------------------------------------------------------------------
cmp_dac_config : spec_serial_dac_arb
generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
val1_i => dac_value,
load1_i => dac_load_p,
val2_i => (others => '0'),
load2_i => '0',
dac_cs_n_o(0) => dac_cs_n_o(0),
dac_cs_n_o(1) => dac_cs_n_o(1),
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- edge detection on the dac_value signal
cmp_dac_value_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => dac_load,
ppulse_o => dac_load_p);
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
......@@ -897,7 +961,7 @@ begin
pulse_i => ext_sync_p,
extended_o => sync_led);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 3c5faced
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 03/08/16 16:14:18
-- Created : 03/14/16 12:32:54
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -46,6 +46,10 @@ entity fmc_masterfip_csr is
mf_adc_prim_conn_n_o : out std_logic;
-- Port for BIT field: 'sec_conn_n' in reg: 'adc'
mf_adc_sec_conn_n_o : out std_logic;
-- Port for std_logic_vector field: 'value' in reg: 'dac'
mf_dac_config_value_o : out std_logic_vector(15 downto 0);
-- Port for BIT field: 'load' in reg: 'dac'
mf_dac_config_load_o : out std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
mf_ext_sync_term_en_o : out std_logic;
-- Port for BIT field: 'transceiver direction' in reg: 'ext sync'
......@@ -397,6 +401,8 @@ signal mf_adc_m5v_shdn_n_int : std_logic ;
signal mf_adc_5v_en_n_int : std_logic ;
signal mf_adc_prim_conn_n_int : std_logic ;
signal mf_adc_sec_conn_n_int : std_logic ;
signal mf_dac_config_value_int : std_logic_vector(15 downto 0);
signal mf_dac_config_load_int : std_logic ;
signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ;
signal mf_ext_sync_oe_int : std_logic ;
......@@ -516,6 +522,8 @@ begin
mf_adc_5v_en_n_int <= '0';
mf_adc_prim_conn_n_int <= '0';
mf_adc_sec_conn_n_int <= '0';
mf_dac_config_value_int <= "0000000000000000";
mf_dac_config_load_int <= '0';
mf_ext_sync_term_en_int <= '0';
mf_ext_sync_dir_int <= '0';
mf_ext_sync_oe_int <= '0';
......@@ -709,6 +717,30 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
if (wb_we_i = '1') then
mf_dac_config_value_int <= wrdata_reg(15 downto 0);
mf_dac_config_load_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= mf_dac_config_value_int;
rddata_reg(16) <= mf_dac_config_load_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then
mf_ext_sync_term_en_int <= wrdata_reg(0);
mf_ext_sync_dir_int <= wrdata_reg(1);
......@@ -750,13 +782,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
when "00000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
when "00000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= mf_speed_i;
......@@ -792,7 +824,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000111" =>
when "00001000" =>
if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31);
......@@ -801,7 +833,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001000" =>
when "00001001" =>
if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31);
......@@ -810,7 +842,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
when "00001010" =>
if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31);
......@@ -819,34 +851,34 @@ begin
rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001010" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001011" =>
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_macrocyc_num_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
when "00001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" =>
when "00001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001110" =>
when "00001111" =>
if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0);
mf_tx_ctrl_start_int <= wrdata_reg(1);
......@@ -871,7 +903,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001111" =>
when "00010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_tx_stat_stop_i;
......@@ -893,27 +925,27 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010000" =>
when "00010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_fd_wdgn_tstamp_i;
rddata_reg(31) <= mf_fd_wdgn_act_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010001" =>
when "00010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_fd_txer_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
when "00010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_fd_txer_tstamp_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
when "00010100" =>
if (wb_we_i = '1') then
mf_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
......@@ -951,7 +983,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010100" =>
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_rx_stat_pream_ok_i;
......@@ -973,7 +1005,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010101" =>
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= mf_rx_stat_curr_byte_indx_i;
......@@ -995,7 +1027,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010110" =>
when "00010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
......@@ -1025,409 +1057,409 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010111" =>
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011000" =>
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011001" =>
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011010" =>
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011011" =>
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011100" =>
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011101" =>
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011110" =>
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011111" =>
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100000" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100001" =>
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100010" =>
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100011" =>
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100100" =>
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100101" =>
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100110" =>
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100111" =>
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101000" =>
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101001" =>
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101010" =>
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101011" =>
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101100" =>
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101101" =>
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101110" =>
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101111" =>
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110000" =>
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110001" =>
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110010" =>
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110011" =>
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
when "01010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
when "01010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010110" =>
when "01010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010111" =>
when "01011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011000" =>
when "01011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011001" =>
when "01011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg67_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011010" =>
when "01011011" =>
if (wb_we_i = '1') then
mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
end if;
......@@ -1458,469 +1490,469 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011011" =>
when "01011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011100" =>
when "01011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011101" =>
when "01011110" =>
if (wb_we_i = '1') then
mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011110" =>
when "01011111" =>
if (wb_we_i = '1') then
mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011111" =>
when "01100000" =>
if (wb_we_i = '1') then
mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
when "01100001" =>
if (wb_we_i = '1') then
mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100001" =>
when "01100010" =>
if (wb_we_i = '1') then
mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100010" =>
when "01100011" =>
if (wb_we_i = '1') then
mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100011" =>
when "01100100" =>
if (wb_we_i = '1') then
mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100100" =>
when "01100101" =>
if (wb_we_i = '1') then
mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100101" =>
when "01100110" =>
if (wb_we_i = '1') then
mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100110" =>
when "01100111" =>
if (wb_we_i = '1') then
mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100111" =>
when "01101000" =>
if (wb_we_i = '1') then
mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101000" =>
when "01101001" =>
if (wb_we_i = '1') then
mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101001" =>
when "01101010" =>
if (wb_we_i = '1') then
mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101010" =>
when "01101011" =>
if (wb_we_i = '1') then
mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101011" =>
when "01101100" =>
if (wb_we_i = '1') then
mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101100" =>
when "01101101" =>
if (wb_we_i = '1') then
mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101101" =>
when "01101110" =>
if (wb_we_i = '1') then
mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101110" =>
when "01101111" =>
if (wb_we_i = '1') then
mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101111" =>
when "01110000" =>
if (wb_we_i = '1') then
mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110000" =>
when "01110001" =>
if (wb_we_i = '1') then
mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110001" =>
when "01110010" =>
if (wb_we_i = '1') then
mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110010" =>
when "01110011" =>
if (wb_we_i = '1') then
mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110011" =>
when "01110100" =>
if (wb_we_i = '1') then
mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110100" =>
when "01110101" =>
if (wb_we_i = '1') then
mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110101" =>
when "01110110" =>
if (wb_we_i = '1') then
mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
when "01110111" =>
if (wb_we_i = '1') then
mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
when "01111000" =>
if (wb_we_i = '1') then
mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
when "01111001" =>
if (wb_we_i = '1') then
mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
when "01111010" =>
if (wb_we_i = '1') then
mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
when "01111011" =>
if (wb_we_i = '1') then
mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
when "01111100" =>
if (wb_we_i = '1') then
mf_tx_data_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
when "01111101" =>
if (wb_we_i = '1') then
mf_tx_data_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
when "01111110" =>
if (wb_we_i = '1') then
mf_tx_data_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
when "01111111" =>
if (wb_we_i = '1') then
mf_tx_data_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
when "10000000" =>
if (wb_we_i = '1') then
mf_tx_data_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
when "10000001" =>
if (wb_we_i = '1') then
mf_tx_data_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
when "10000010" =>
if (wb_we_i = '1') then
mf_tx_data_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
when "10000011" =>
if (wb_we_i = '1') then
mf_tx_data_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
when "10000100" =>
if (wb_we_i = '1') then
mf_tx_data_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
when "10000101" =>
if (wb_we_i = '1') then
mf_tx_data_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
when "10000110" =>
if (wb_we_i = '1') then
mf_tx_data_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
when "10000111" =>
if (wb_we_i = '1') then
mf_tx_data_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
when "10001000" =>
if (wb_we_i = '1') then
mf_tx_data_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
when "10001001" =>
if (wb_we_i = '1') then
mf_tx_data_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
when "10001010" =>
if (wb_we_i = '1') then
mf_tx_data_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
when "10001011" =>
if (wb_we_i = '1') then
mf_tx_data_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
when "10001100" =>
if (wb_we_i = '1') then
mf_tx_data_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
when "10001101" =>
if (wb_we_i = '1') then
mf_tx_data_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
when "10001110" =>
if (wb_we_i = '1') then
mf_tx_data_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
when "10001111" =>
if (wb_we_i = '1') then
mf_tx_data_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
when "10010000" =>
if (wb_we_i = '1') then
mf_tx_data_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
when "10010001" =>
if (wb_we_i = '1') then
mf_tx_data_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
when "10010010" =>
if (wb_we_i = '1') then
mf_tx_data_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
when "10010011" =>
if (wb_we_i = '1') then
mf_tx_data_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
when "10010100" =>
if (wb_we_i = '1') then
mf_tx_data_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
when "10010101" =>
if (wb_we_i = '1') then
mf_tx_data_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
when "10010110" =>
if (wb_we_i = '1') then
mf_tx_data_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
when "10010111" =>
if (wb_we_i = '1') then
mf_tx_data_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
when "10011000" =>
if (wb_we_i = '1') then
mf_tx_data_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011000" =>
when "10011001" =>
if (wb_we_i = '1') then
mf_tx_data_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011001" =>
when "10011010" =>
if (wb_we_i = '1') then
mf_tx_data_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011010" =>
when "10011011" =>
if (wb_we_i = '1') then
mf_tx_data_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011011" =>
when "10011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011100" =>
when "10011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg66_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg66_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011101" =>
when "10011110" =>
if (wb_we_i = '1') then
mf_tx_data_reg67_int <= wrdata_reg(31 downto 0);
end if;
......@@ -1959,6 +1991,10 @@ begin
mf_adc_prim_conn_n_o <= mf_adc_prim_conn_n_int;
-- sec_conn_n
mf_adc_sec_conn_n_o <= mf_adc_sec_conn_n_int;
-- value
mf_dac_config_value_o <= mf_dac_config_value_int;
-- load
mf_dac_config_load_o <= mf_dac_config_load_int;
-- termination enable
mf_ext_sync_term_en_o <= mf_ext_sync_term_en_int;
-- transceiver direction
......
rtl/masterFIP_pkg.vhd
View file @ 3c5faced
......@@ -204,6 +204,9 @@ package masterFIP_pkg is
mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic;
mf_dac_config_value_o : out std_logic_vector(15 downto 0);
mf_dac_config_load_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic;
......@@ -412,6 +415,9 @@ package masterFIP_pkg is
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
aux_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 3c5faced
......@@ -3,7 +3,7 @@
* File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 03/08/16 16:14:19
* Created : 03/14/16 12:32:55
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -66,6 +66,17 @@
/* definitions for field: sec_conn_n in reg: adc */
#define MF_ADC_SEC_CONN_N WBGEN2_GEN_MASK(9, 1)
/* definitions for register: dac */
/* definitions for field: value in reg: dac */
#define MF_DAC_CONFIG_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define MF_DAC_CONFIG_VALUE_SHIFT 0
#define MF_DAC_CONFIG_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MF_DAC_CONFIG_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: load in reg: dac */
#define MF_DAC_CONFIG_LOAD WBGEN2_GEN_MASK(16, 1)
/* definitions for register: ext sync */
/* definitions for field: termination enable in reg: ext sync */
......@@ -474,312 +485,314 @@
#define MF_REG_DBG 0x00000008
/* [0xc]: REG adc */
#define MF_REG_ADC 0x0000000c
/* [0x10]: REG ext sync */
#define MF_REG_EXT_SYNC 0x00000010
/* [0x14]: REG ext sync pulses cnt */
#define MF_REG_EXT_SYNC_P_CNT 0x00000014
/* [0x18]: REG bus speed */
#define MF_REG_SPEED 0x00000018
/* [0x1c]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x0000001c
/* [0x20]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000020
/* [0x24]: REG silence lgth */
#define MF_REG_SILEN 0x00000024
/* [0x28]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x00000028
/* [0x2c]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x0000002c
/* [0x30]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000030
/* [0x34]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x00000034
/* [0x38]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x00000038
/* [0x3c]: REG tx status */
#define MF_REG_TX_STAT 0x0000003c
/* [0x40]: REG fieldrive wdgn */
#define MF_REG_FD_WDGN 0x00000040
/* [0x44]: REG fieldrive txer cnt */
#define MF_REG_FD_TXER_CNT 0x00000044
/* [0x48]: REG fieldrive txer tstamp */
#define MF_REG_FD_TXER_TSTAMP 0x00000048
/* [0x4c]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x0000004c
/* [0x50]: REG rx status */
#define MF_REG_RX_STAT 0x00000050
/* [0x54]: REG rx status current byte index */
#define MF_REG_RX_STAT_CURR_BYTE_INDX 0x00000054
/* [0x58]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x00000058
/* [0x5c]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x0000005c
/* [0x60]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x00000060
/* [0x64]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x00000064
/* [0x68]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x00000068
/* [0x6c]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x0000006c
/* [0x70]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x00000070
/* [0x74]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x00000074
/* [0x78]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x00000078
/* [0x7c]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x0000007c
/* [0x80]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x00000080
/* [0x84]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x00000084
/* [0x88]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x00000088
/* [0x8c]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x0000008c
/* [0x90]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x00000090
/* [0x94]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x00000094
/* [0x98]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x00000098
/* [0x9c]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x0000009c
/* [0xa0]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x000000a0
/* [0xa4]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x000000a4
/* [0xa8]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000a8
/* [0xac]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000ac
/* [0xb0]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000b0
/* [0xb4]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000b4
/* [0xb8]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000b8
/* [0xbc]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000bc
/* [0xc0]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000c0
/* [0xc4]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000c4
/* [0xc8]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000c8
/* [0xcc]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000cc
/* [0xd0]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000d0
/* [0xd4]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000d4
/* [0xd8]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000d8
/* [0xdc]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000dc
/* [0xe0]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000e0
/* [0xe4]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000e4
/* [0xe8]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x000000e8
/* [0xec]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x000000ec
/* [0xf0]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x000000f0
/* [0xf4]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x000000f4
/* [0xf8]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x000000f8
/* [0xfc]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x000000fc
/* [0x100]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x00000100
/* [0x104]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x00000104
/* [0x108]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x00000108
/* [0x10c]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x0000010c
/* [0x110]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x00000110
/* [0x114]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x00000114
/* [0x118]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x00000118
/* [0x11c]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x0000011c
/* [0x120]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x00000120
/* [0x124]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x00000124
/* [0x128]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x00000128
/* [0x12c]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x0000012c
/* [0x130]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x00000130
/* [0x134]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x00000134
/* [0x138]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x00000138
/* [0x13c]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x0000013c
/* [0x140]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x00000140
/* [0x144]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x00000144
/* [0x148]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x00000148
/* [0x14c]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x0000014c
/* [0x150]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x00000150
/* [0x154]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x00000154
/* [0x158]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x00000158
/* [0x15c]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x0000015c
/* [0x160]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x00000160
/* [0x164]: REG rx data reg67 */
#define MF_REG_RX_DATA_REG67 0x00000164
/* [0x168]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x00000168
/* [0x16c]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x0000016c
/* [0x170]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000170
/* [0x174]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x00000174
/* [0x178]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x00000178
/* [0x17c]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x0000017c
/* [0x180]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000180
/* [0x184]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x00000184
/* [0x188]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x00000188
/* [0x18c]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x0000018c
/* [0x190]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x00000190
/* [0x194]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x00000194
/* [0x198]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x00000198
/* [0x19c]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x0000019c
/* [0x1a0]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x000001a0
/* [0x1a4]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x000001a4
/* [0x1a8]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x000001a8
/* [0x1ac]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001ac
/* [0x1b0]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001b0
/* [0x1b4]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001b4
/* [0x1b8]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001b8
/* [0x1bc]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001bc
/* [0x1c0]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001c0
/* [0x1c4]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001c4
/* [0x1c8]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001c8
/* [0x1cc]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001cc
/* [0x1d0]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001d0
/* [0x1d4]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001d4
/* [0x1d8]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001d8
/* [0x1dc]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001dc
/* [0x1e0]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001e0
/* [0x1e4]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001e4
/* [0x1e8]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x000001e8
/* [0x1ec]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x000001ec
/* [0x1f0]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x000001f0
/* [0x1f4]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x000001f4
/* [0x1f8]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x000001f8
/* [0x1fc]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x000001fc
/* [0x200]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x00000200
/* [0x204]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x00000204
/* [0x208]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x00000208
/* [0x20c]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x0000020c
/* [0x210]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000210
/* [0x214]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x00000214
/* [0x218]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x00000218
/* [0x21c]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x0000021c
/* [0x220]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000220
/* [0x224]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x00000224
/* [0x228]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x00000228
/* [0x22c]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x0000022c
/* [0x230]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000230
/* [0x234]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x00000234
/* [0x238]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x00000238
/* [0x23c]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x0000023c
/* [0x240]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000240
/* [0x244]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x00000244
/* [0x248]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x00000248
/* [0x24c]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x0000024c
/* [0x250]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000250
/* [0x254]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x00000254
/* [0x258]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x00000258
/* [0x25c]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x0000025c
/* [0x260]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000260
/* [0x264]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x00000264
/* [0x268]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x00000268
/* [0x26c]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x0000026c
/* [0x270]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000270
/* [0x274]: REG tx data reg67 */
#define MF_REG_TX_DATA_REG67 0x00000274
/* [0x10]: REG dac */
#define MF_REG_DAC_CONFIG 0x00000010
/* [0x14]: REG ext sync */
#define MF_REG_EXT_SYNC 0x00000014
/* [0x18]: REG ext sync pulses cnt */
#define MF_REG_EXT_SYNC_P_CNT 0x00000018
/* [0x1c]: REG bus speed */
#define MF_REG_SPEED 0x0000001c
/* [0x20]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x00000020
/* [0x24]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000024
/* [0x28]: REG silence lgth */
#define MF_REG_SILEN 0x00000028
/* [0x2c]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x0000002c
/* [0x30]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x00000030
/* [0x34]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000034
/* [0x38]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x00000038
/* [0x3c]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x0000003c
/* [0x40]: REG tx status */
#define MF_REG_TX_STAT 0x00000040
/* [0x44]: REG fieldrive wdgn */
#define MF_REG_FD_WDGN 0x00000044
/* [0x48]: REG fieldrive txer cnt */
#define MF_REG_FD_TXER_CNT 0x00000048
/* [0x4c]: REG fieldrive txer tstamp */
#define MF_REG_FD_TXER_TSTAMP 0x0000004c
/* [0x50]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x00000050
/* [0x54]: REG rx status */
#define MF_REG_RX_STAT 0x00000054
/* [0x58]: REG rx status current byte index */
#define MF_REG_RX_STAT_CURR_BYTE_INDX 0x00000058
/* [0x5c]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x0000005c
/* [0x60]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x00000060
/* [0x64]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x00000064
/* [0x68]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x00000068
/* [0x6c]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x0000006c
/* [0x70]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x00000070
/* [0x74]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x00000074
/* [0x78]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x00000078
/* [0x7c]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x0000007c
/* [0x80]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x00000080
/* [0x84]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x00000084
/* [0x88]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x00000088
/* [0x8c]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x0000008c
/* [0x90]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x00000090
/* [0x94]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x00000094
/* [0x98]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x00000098
/* [0x9c]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x0000009c
/* [0xa0]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x000000a0
/* [0xa4]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x000000a4
/* [0xa8]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x000000a8
/* [0xac]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000ac
/* [0xb0]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000b0
/* [0xb4]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000b4
/* [0xb8]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000b8
/* [0xbc]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000bc
/* [0xc0]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000c0
/* [0xc4]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000c4
/* [0xc8]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000c8
/* [0xcc]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000cc
/* [0xd0]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000d0
/* [0xd4]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000d4
/* [0xd8]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000d8
/* [0xdc]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000dc
/* [0xe0]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000e0
/* [0xe4]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000e4
/* [0xe8]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000e8
/* [0xec]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x000000ec
/* [0xf0]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x000000f0
/* [0xf4]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x000000f4
/* [0xf8]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x000000f8
/* [0xfc]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x000000fc
/* [0x100]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x00000100
/* [0x104]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x00000104
/* [0x108]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x00000108
/* [0x10c]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x0000010c
/* [0x110]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x00000110
/* [0x114]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x00000114
/* [0x118]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x00000118
/* [0x11c]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x0000011c
/* [0x120]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x00000120
/* [0x124]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x00000124
/* [0x128]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x00000128
/* [0x12c]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x0000012c
/* [0x130]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x00000130
/* [0x134]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x00000134
/* [0x138]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x00000138
/* [0x13c]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x0000013c
/* [0x140]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x00000140
/* [0x144]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x00000144
/* [0x148]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x00000148
/* [0x14c]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x0000014c
/* [0x150]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x00000150
/* [0x154]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x00000154
/* [0x158]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x00000158
/* [0x15c]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x0000015c
/* [0x160]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x00000160
/* [0x164]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x00000164
/* [0x168]: REG rx data reg67 */
#define MF_REG_RX_DATA_REG67 0x00000168
/* [0x16c]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x0000016c
/* [0x170]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x00000170
/* [0x174]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000174
/* [0x178]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x00000178
/* [0x17c]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x0000017c
/* [0x180]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x00000180
/* [0x184]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000184
/* [0x188]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x00000188
/* [0x18c]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x0000018c
/* [0x190]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x00000190
/* [0x194]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x00000194
/* [0x198]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x00000198
/* [0x19c]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x0000019c
/* [0x1a0]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x000001a0
/* [0x1a4]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x000001a4
/* [0x1a8]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x000001a8
/* [0x1ac]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x000001ac
/* [0x1b0]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001b0
/* [0x1b4]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001b4
/* [0x1b8]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001b8
/* [0x1bc]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001bc
/* [0x1c0]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001c0
/* [0x1c4]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001c4
/* [0x1c8]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001c8
/* [0x1cc]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001cc
/* [0x1d0]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001d0
/* [0x1d4]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001d4
/* [0x1d8]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001d8
/* [0x1dc]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001dc
/* [0x1e0]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001e0
/* [0x1e4]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001e4
/* [0x1e8]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001e8
/* [0x1ec]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x000001ec
/* [0x1f0]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x000001f0
/* [0x1f4]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x000001f4
/* [0x1f8]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x000001f8
/* [0x1fc]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x000001fc
/* [0x200]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x00000200
/* [0x204]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x00000204
/* [0x208]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x00000208
/* [0x20c]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x0000020c
/* [0x210]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x00000210
/* [0x214]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000214
/* [0x218]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x00000218
/* [0x21c]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x0000021c
/* [0x220]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x00000220
/* [0x224]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000224
/* [0x228]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x00000228
/* [0x22c]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x0000022c
/* [0x230]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x00000230
/* [0x234]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000234
/* [0x238]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x00000238
/* [0x23c]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x0000023c
/* [0x240]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x00000240
/* [0x244]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000244
/* [0x248]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x00000248
/* [0x24c]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x0000024c
/* [0x250]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x00000250
/* [0x254]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000254
/* [0x258]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x00000258
/* [0x25c]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x0000025c
/* [0x260]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x00000260
/* [0x264]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000264
/* [0x268]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x00000268
/* [0x26c]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x0000026c
/* [0x270]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x00000270
/* [0x274]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000274
/* [0x278]: REG tx data reg67 */
#define MF_REG_TX_DATA_REG67 0x00000278
#endif
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 3c5faced
This source diff could not be displayed because it is too large. You can view the blob instead.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 3c5faced
......@@ -140,7 +140,36 @@ peripheral {
};
-------------------------------------------------------------------------------
-- DAC configuration --
-------------------------------------------------------------------------------
reg {
name = "dac";
prefix = "dac_config";
field {
name = "value";
prefix = "value";
description = "Vout= Vref (value/ 65536)\
For the DAC middle range: value = 32768 = 0x8000";
type = SLV;
size = 16;
-- add reset value = "0x8000";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "load";
prefix = "load";
description = "upon rising edge, the value is transferred to the dac";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- external synch --
-------------------------------------------------------------------------------
......
sim/spec/data_vectors/board_settings_config.txt
View file @ 3c5faced
......@@ -9,6 +9,6 @@ vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1)
1 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
View file @ 3c5faced
......@@ -44,8 +44,8 @@ wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 000000000003001C F 80004880
wait %d20
--wr 000000000003001C F 80004880
--wait %d20
--wr 000000000003001C F 00002A6D
-- turnar counter top
......@@ -60,111 +60,109 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030038 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030160 F 00000003
wr 000000000003016C F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030164 F 00000305
wr 0000000000030170 F 00000305
wait %d20
-- tx_start
wr 0000000000030038 F 00000202
wr 000000000003003C F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000030038 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030160 F 00000002
wr 000000000003016C F 00000002
wait %d20
-- data bytes
wr 0000000000030164 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030170 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 0000000000030168 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wr 0000000000030174 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 0000000000030038 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030038 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030160 F 00000003
wr 000000000003016C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030164 F 00000314
wr 0000000000030170 F 00000306 -------------------------0314
wait %d20
-- tx_start
wr 0000000000030038 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030044 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030050 F 00000002
rd 0000000000030054 F 00000002
wait %d20
rd 0000000000030044 F 03800550
rd 0000000000030048 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030038 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030160 F 00000003
wr 000000000003016C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030164 F 00000306
wr 0000000000030168 F 00000306
wait %d20
-- tx_start
wr 0000000000030038 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030038 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030044 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030050 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030054 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 0000000000030054 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000003005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
......@@ -172,6 +170,8 @@ rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
......@@ -236,7 +236,7 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 000000000003015C F 00000040
wr 000000000003016C F 00000040
wait %d20
-- rx_rst
......@@ -244,5 +244,5 @@ wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 0000000000030038 F 00000002
wr 000000000003003C F 00000002
wait %d20000
\ No newline at end of file
sim/spec/data_vectors/user_sequence.txt
View file @ 3c5faced
......@@ -5,7 +5,7 @@
0,1,8,0,0 -- reading VAR1 from memory
350 us -- stand-by time
1,3,8,0,0 -- writting VAR3 in memory
20383 us -- stand-by time
20383 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
431 us -- stand-by time
......
sim/spec/testbench/nanoFIP_lib/wf_crc.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_crc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_crc.vhd |
-- |
-- Description The unit creates the modules for: |
-- o the generation of the CRC of serial data, |
-- o the verification of an incoming CRC syndrome. |
-- The unit is instantiated in both the wf_fd_transmitter, for the generation of the |
-- FCS field of produced RP_DAT frames, and the wf_fd_receiver for the validation of |
-- of an incoming ID_DAT or consumed RP_DAT frame. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Date 23/02/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
-- wf_rx_deserializer |
-- wf_tx_serializer |
---------------- |
-- Last changes |
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content |
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, |
-- variable v_q_check_mask replaced with a signal, |
-- code cleaned-up+commented |
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! |
-- xor replaced with if(Syndrome_Verification); processes rewritten; |
-- delay on data_bit_ready_p_i removed. |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_crc
--=================================================================================================
entity wf_crc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_rx_deserializer/ wf_tx_serializer units
data_bit_i : in std_logic; -- incoming data bit stream
data_bit_ready_p_i : in std_logic; -- indicates the sampling moment of data_bit_i
start_crc_p_i : in std_logic; -- beginning of the CRC calculation
-- OUTPUTS
-- Signal to the wf_rx_deserializer unit
crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome
-- Signal to the wf_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC
end entity wf_crc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_crc is
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- CRC Calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
-- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
-- are interconnected as a linear feedback shift register.
Generate_16_bit_Register_and_Interconnections:
s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process CRC_calculation: the process "moves" the shift register described
-- above, for the calculation of the CRC.
CRC_calculation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_q <= (others => '0');
else
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to the Annex)
elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
end if;
end if;
end if;
end process;
-- -- -- -- --
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
-- During reception, the CRC is being calculated as data is arriving (same as in the transmission)
-- and at the same time it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC
-- calculated from the received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC
-- word has been received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to |
-- counter_top_i; initial value after reset is all '1'; |
-- counter_decr_p_i renamed to counter_decr_i |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_decr_counter
--=================================================================================================
entity wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i : in std_logic; -- resets counter to all '1'
-- Signals from any unit
counter_decr_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i
counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end entity wf_decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_rst_i = '1' then
s_counter <= (others => '1');
else
if counter_load_i = '1' then
s_counter <= counter_top_i;
elsif counter_decr_i = '1' then
s_counter <= s_counter - 1;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_incr_counter
--=================================================================================================
entity wf_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity wf_incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_package.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- WF_PACKAGE |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.05 |
---------------- |
-- Last changes |
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) |
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of |
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up |
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs |
-- added DualClkRam |
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- 11/2011 v0.06 EG c_SESSION_TIMEOUT_C_LGTH, c_JTAG_TIMEOUT_C_LGTH added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Package declaration for wf_package
--=================================================================================================
package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant c_QUARTZ_PERIOD : real := 25.0;
---------------------------------------------------------------------------------------------------
-- Constants regarding the JTAG controller --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent
-- in one frame: 122 bytes * 8 bits
constant c_FOUR_JC_TCK_C_LGTH : natural := 5; -- length of a counter counting 4 JC_TCK periods;
-- the JC_TCK frequency is defined by this constant.
-- ex: 5 MHz JC_TCK period = 200 ns = 4 uclk periods,
-- 4 JC_TCK periods = 16 uclk, hence 5 bits counter.
-- Use c_FOUR_JC_TCK_C_LGTH = 6 for a 2.5 MHz JC_TCK,
-- c_FOUR_JC_TCK_C_LGTH = 7 for 1.25 MHz etc.
-- check also the c_JC_TIMEOUT_C_LGTH in the following paragraph
---------------------------------------------------------------------------------------------------
-- Constants regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- To add a robust layer of protection to the FSMs of the design, counters that depend only on
-- the system clock have being implemented; when they are filled up, they can bring the FSMs back
-- to the IDLE state.
-- For the wf_rx_deserializer, at the slowest bit rate, 31.25 kbps, the reception of the longest
-- frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- Similarly, for the wf_tx_serializer, at the slowest bit rate, 31.25 kbps, the transmission of
-- the longest frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- For the wf_engine_control, at the slowest bit rate, 31.25 kbps, the reception of an ID_DAT frame
-- followed by the reception/ transmission of an RP_DAT should not last more than:
-- 8 bytes ID_DAT = 2048 us
-- silence time = 4096 us
-- 133 bytes RP_DAT = 34048 us
-- ------------
-- 40192 us
-- This also demands for a 21 bits counter.
-- Therefore the same length of the timeout counters can be used for the FSMs of the wf_rx_deserializer,
-- wf_tx_serializer and wf_engine_control. The FSMs will be reset if 52 ms (complete 21 bit counter)
-- have passed since they have left the IDLE state.
constant c_SESSION_TIMEOUT_C_LGTH : natural := 21;
---------------------------------------------------------------------------------------------------
-- For the wf_jtag_controller FSM this timeout depends on the frequency of the JC_TCK.
-- The time the FSM needs to handle the biggest frame (122 bytes) is:
-- 122 * ((4 * JC_TCK_period) + 2 uclk_period)
-- For a 5 MHz JC_TCK this is 103.7 us and demands for a counter of 13 bits.
-- Use c_JC_TIMEOUT_C_LGTH = 13 also for a 2.5 MHz JC_TCK,
-- c_JC_TIMEOUT_C_LGTH = 14 for 1.25 MHz etc.
constant c_JC_TIMEOUT_C_LGTH : natural := 13;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
constant c_DEGLITCH_THRESHOLD : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constant regarding the frame structure --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BYTES : natural := 130; -- maximum number of bytes in a frame after the
-- FSS (counting starts from 0!)
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculation --
---------------------------------------------------------------------------------------------------
constant c_CRC_POLY_LGTH : natural := 16;
constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110111001111";
constant c_CRC_VERIF_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110001101011";
---------------------------------------------------------------------------------------------------
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant c_VP : std_logic_vector (1 downto 0) := "11";
constant c_VN : std_logic_vector (1 downto 0) := "00";
constant c_ONE : std_logic_vector (1 downto 0) := "10";
constant c_ZERO : std_logic_vector (1 downto 0) := "01";
constant c_PRE : std_logic_vector (15 downto 0) := c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
constant c_FES : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
constant c_FSS : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
---------------------------------------------------------------------------------------------------
-- Constants regarding the CTRL and PDU_TYPE bytes of ID_DAT and RP_DAT frames --
---------------------------------------------------------------------------------------------------
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (5 downto 0) := "000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (5 downto 0) := "000010";
constant c_RP_DAT_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "000110";
constant c_RP_DAT_RQ1_CTRL_BYTE : std_logic_vector (5 downto 0) := "101010";
constant c_RP_DAT_RQ2_CTRL_BYTE : std_logic_vector (5 downto 0) := "001010";
constant c_RP_DAT_RQ1_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "101110";
constant c_RP_DAT_RQ2_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "001110";
constant c_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
---------------------------------------------------------------------------------------------------
-- Constants regarding the nanoFIP status bits --
---------------------------------------------------------------------------------------------------
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_TLER_INDEX : integer := 4;
constant c_R_FCSER_INDEX : integer := 5;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Transmitter --
---------------------------------------------------------------------------------------------------
constant c_TX_SCHED_BUFF_LGTH : natural := 4; -- length of the buffer of pulses used for
-- the transmission synchronization
---------------------------------------------------------------------------------------------------
-- Constants regarding the MPS status bits --
---------------------------------------------------------------------------------------------------
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the P3_LGTH[2:0] settings --
---------------------------------------------------------------------------------------------------
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(7 downto 0) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010"); -- reserved
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the bit rate --
---------------------------------------------------------------------------------------------------
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
constant c_2_PERIODS_COUNTER_LGTH : natural := 12; -- length of a counter counting 2 reception/
-- transmission periods
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the turnaround and silence times --
---------------------------------------------------------------------------------------------------
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
type t_timeouts is
record
turnaround : integer;
silence : integer;
end record;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_RESERVE_INDEX : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (4096000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (13500.0 / c_QUARTZ_PERIOD),
silence => integer (96000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (4096000.0 /C_QUARTZ_PERIOD)));
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the consumed & produced variables --
---------------------------------------------------------------------------------------------------
-- Construction of a table that groups main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
type t_var_record is record
var : t_var;
hexvalue : std_logic_vector (7 downto 0);
prod_or_cons : std_logic_vector (1 downto 0);
broadcast : std_logic;
base_addr : unsigned (8 downto 0);
array_lgth : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
end record;
type t_var_array is array (natural range <>) of t_var_record;
constant c_VAR_PRESENCE_INDEX : integer := 0;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
constant c_VAR_1_INDEX : integer := 3;
constant c_VAR_2_INDEX : integer := 4;
constant c_VAR_RST_INDEX : integer := 5;
constant c_VAR_4_INDEX : integer := 6;
constant c_VAR_5_INDEX : integer := 7;
constant c_VARS_ARRAY : t_var_array(0 to 7) :=
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000111", -- 8 bytes in total including the CTRL byte
-- (counting starts from 0;-))
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
7 => x"00", others => x"ff")),
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00001010", -- 11 bytes in total including the CTRL byte
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00" , 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
others => x"ff")),
c_VAR_3_INDEX => (var => var_3,
hexvalue => x"06",
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
array_lgth => "00000001", -- only the CTRL and PDU_TYPE bytes are
-- predefined
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"91",
prod_or_cons => "01",
broadcast => '1',
base_addr => "010000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_4_INDEX => (var => var_4,
hexvalue => x"aa",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_5_INDEX => (var => var_5,
hexvalue => x"ab",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000101", -- 6 bytes in total: CTRL, PDU_TYPE, LGTH,
-- 1 byte of data, nFIP status and MPS bytes
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff"))); -- only the CTRL and PDU_TYPE bytes
-- are predefined
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component wf_rx_deserializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rx_rst_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
fd_rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
-----------------------------------------------------------------
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
crc_wrong_p_o : out std_logic;
fss_crc_fes_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
end component wf_rx_deserializer;
---------------------------------------------------------------------------------------------------
component wf_tx_serializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
tx_start_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_sched_p_buff_i : in std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0);
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
tx_osc_rst_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component wf_tx_serializer;
---------------------------------------------------------------------------------------------------
component wf_cons_bytes_processor
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
-----------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
jc_mem_data_o : out std_logic_vector (7 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_cons_bytes_processor;
---------------------------------------------------------------------------------------------------
component wf_consumption is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_rst_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
cons_bytes_excess_i : in std_logic;
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
jc_start_p_o : out std_logic;
data_o : out std_logic_vector (15 downto 0);
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
jc_mem_data_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_consumption;
---------------------------------------------------------------------------------------------------
component wf_jtag_controller is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
jc_mem_data_i : in std_logic_vector (7 downto 0);
jc_start_p_i : in std_logic;
jc_tdo_i : in std_logic;
-----------------------------------------------------------------
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic;
jc_tdo_byte_o : out std_logic_vector (7 downto 0);
--TP39 : out std_logic;
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));
-----------------------------------------------------------------
end component wf_jtag_controller;
---------------------------------------------------------------------------------------------------
component wf_fd_receiver is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
nfip_rst_i : in std_logic;
rx_rst_i : in std_logic;
-----------------------------------------------------------------
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
-----------------------------------------------------------------
end component wf_fd_receiver;
---------------------------------------------------------------------------------------------------
component wf_rx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_edge_p_i : in std_logic;
rx_osc_rst_i : in std_logic;
-----------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic );
-----------------------------------------------------------------
end component wf_rx_osc;
---------------------------------------------------------------------------------------------------
component wf_production is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
constr_id_dec_i : in std_logic_vector (7 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
byte_o : out std_logic_vector (7 downto 0);
u_cacer_o : out std_logic;
r_fcser_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component wf_production;
---------------------------------------------------------------------------------------------------
component wf_fd_transmitter is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_byte_i : in std_logic_vector (7 downto 0);
tx_byte_request_accept_p_i : in std_logic;
tx_last_data_byte_p_i : in std_logic;
tx_start_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
end component wf_fd_transmitter;
---------------------------------------------------------------------------------------------------
component wf_tx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_osc_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_clk_o : out std_logic;
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-----------------------------------------------------------------
end component wf_tx_osc;
---------------------------------------------------------------------------------------------------
component wf_prod_bytes_retriever is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_lgth_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_prod_bytes_retriever;
---------------------------------------------------------------------------------------------------
component wf_engine_control
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_byte_request_p_i : in std_logic;
tx_completed_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_ok_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_accept_p_o : out std_logic;
tx_last_data_byte_p_o : out std_logic;
tx_start_p_o : out std_logic;
prod_byte_index_o : out std_logic_vector (7 downto 0);
cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_lgth_o : out std_logic_vector (7 downto 0);
cons_bytes_excess_o : out std_logic;
rx_rst_o : out std_logic;
var_o : out t_var);
-----------------------------------------------------------------
end component wf_engine_control;
---------------------------------------------------------------------------------------------------
component wf_reset_unit
port (
uclk_i : in std_logic;
wb_clk_i : in std_logic;
rstin_a_i : in std_logic;
rstpon_a_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-----------------------------------------------------------------
wb_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
rston_o : out std_logic;
fd_rstn_o : out std_logic);
-----------------------------------------------------------------
end component wf_reset_unit;
---------------------------------------------------------------------------------------------------
component wf_dualram_512x8_clka_rd_clkb_wr
port (
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (8 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-----------------------------------------------------------------
data_porta_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_dualram_512x8_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component dualram_512x8 is
port (
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
-----------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component dualram_512x8;
---------------------------------------------------------------------------------------------------
component wf_crc
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_crc_p_i : in std_logic;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
-----------------------------------------------------------------
crc_ok_p_o : out std_logic;
crc_o : out std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0));
-----------------------------------------------------------------
end component wf_crc;
---------------------------------------------------------------------------------------------------
component wf_manch_encoder is
generic (g_word_lgth : natural);
port (
word_i : in std_logic_vector (g_word_lgth-1 downto 0);
-----------------------------------------------------------------
word_manch_o : out std_logic_vector ((2*g_word_lgth)-1 downto 0));
-----------------------------------------------------------------
end component wf_manch_encoder;
---------------------------------------------------------------------------------------------------
component wf_rx_deglitcher
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
fd_rxd_a_i : in std_logic;
-----------------------------------------------------------------
fd_rxd_filt_o : out std_logic;
fd_rxd_filt_edge_p_o : out std_logic;
fd_rxd_filt_f_edge_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_rx_deglitcher;
---------------------------------------------------------------------------------------------------
component wf_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_p_i : in std_logic;
var_i : in t_var;
-----------------------------------------------------------------
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_status_bytes_gen;
---------------------------------------------------------------------------------------------------
component wf_bits_to_txd
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
txd_bit_index_i : in unsigned (4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_fss_i : in std_logic;
sending_data_i : in std_logic;
sending_crc_i : in std_logic;
sending_fes_i : in std_logic;
stop_transmission_i : in std_logic;
tx_clk_p_i : in std_logic;
-----------------------------------------------------------------
txd_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component wf_bits_to_txd;
---------------------------------------------------------------------------------------------------
component nanofip
port (
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
rstin_i : in std_logic;
rstpon_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
wb_clk_i : in std_logic;
dat_i : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector (9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
jc_tdo_i : in std_logic;
-----------------------------------------------------------------
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector (15 downto 0);
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic);
-----------------------------------------------------------------
end component nanofip;
---------------------------------------------------------------------------------------------------
component wf_model_constr_decoder
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
-----------------------------------------------------------------
s_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_model_constr_decoder;
---------------------------------------------------------------------------------------------------
component wf_decr_counter is
generic (g_counter_lgth : natural := 5);
port (
uclk_i : in std_logic;
counter_rst_i : in std_logic;
counter_top_i : in unsigned (g_counter_lgth-1 downto 0);
counter_load_i : in std_logic;
counter_decr_i : in std_logic;
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_zero_o : out std_logic);
-----------------------------------------------------------------
end component wf_decr_counter;
---------------------------------------------------------------------------------------------------
component wf_incr_counter is
generic (g_counter_lgth : natural := 8);
port (
uclk_i : in std_logic;
counter_reinit_i : in std_logic;
counter_incr_i : in std_logic;
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
-----------------------------------------------------------------
end component wf_incr_counter;
---------------------------------------------------------------------------------------------------
component wf_prod_data_lgth_calc is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
-----------------------------------------------------------------
prod_data_lgth_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component wf_cons_outcome is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
cons_bytes_excess_i : in std_logic;
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
jc_start_p_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_cons_outcome;
---------------------------------------------------------------------------------------------------
component wf_prod_permit is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
-----------------------------------------------------------------
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component wf_prod_permit;
---------------------------------------------------------------------------------------------------
component wf_wb_controller is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_id_i : in std_logic_vector (2 downto 0);
-----------------------------------------------------------------
wb_ack_prod_p_o : out std_logic;
wb_ack_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_wb_controller;
---------------------------------------------------------------------------------------------------
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end wf_package;
--=================================================================================================
-- package body
--=================================================================================================
package body wf_package is
---------------------------------------------------------------------------------------------------
-- Function for the encoding of a word to its Manchester 2 (manch.) equivalent.
-- Each bit "1" is replaced by "10" and each bit "0" by "01".
-- The manch. encoding ensures that there is one transition for each bit.
-- o bit : "0" "1"
-- o manch. encoded : "0 1" "1 0"
-- o scheme : _|- -|_
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector ((2*word_i'length) -1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
-----------------------------------------------------------------
return word_manch_o;
-----------------------------------------------------------------
end function;
end wf_package;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_deglitcher |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_deglitcher.vhd |
-- |
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. |
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.03 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content |
-- 23/08/2010 v0.02 EG code cleaned-up+commented |
-- 14/02/2011 v0.03 EG complete change, no dependency on osc; |
-- fd_rxd deglitched right at reception |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deglitcher
--=================================================================================================
entity wf_rx_deglitcher is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; -- receiver data
-- OUTPUTS
-- Signals to the wf_rx_deserializer unit
fd_rxd_filt_o : out std_logic; -- filtered output signal
fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal
fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal
end wf_rx_deglitcher;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_deglitcher is
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic;
signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic;
signal s_filt_c : unsigned (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_RXD synchronization --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
-- FD_RXD to the uclk, using a set of 2 registers.
FD_RXD_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_rxd_synch <= (others => '0');
else
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Deglitching --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only
-- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits.
-- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
FD_RXD_deglitcher: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
s_fd_rxd_filt <= '0';
s_fd_rxd_filt_d1 <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if s_fd_rxd_synch(1) = '0' then -- arrival of a '0'
if s_filt_c /= 0 then -- counter updated
s_filt_c <= s_filt_c - 1;
else
s_fd_rxd_filt <= '0'; -- output updated
end if; -- if counter = 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1'
if s_filt_c /= c_DEGLITCH_THRESHOLD then
s_filt_c <= s_filt_c + 1; -- counter updated
else
s_fd_rxd_filt <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD
end if;
s_fd_rxd_filt_d1 <= s_fd_rxd_filt; -- used for the edges detection
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
s_fd_rxd_filt_r_edge_p <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection
-- of a falling edge
s_fd_rxd_filt_f_edge_p <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection
-- of a rising edge
fd_rxd_filt_edge_p_o <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p;
fd_rxd_filt_f_edge_p_o <= s_fd_rxd_filt_f_edge_p;
fd_rxd_filt_o <= s_fd_rxd_filt;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_deserializer |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_deserializer.vhd |
-- |
-- Description De-serialization of the deglitched "nanoFIP FIELDRIVE" input signal FD_RXD and |
-- construction of bytes of data to be provided to: |
-- o the wf_engine_control unit, for the contents of ID_DAT frames |
-- o the wf_consumption unit, for the contents of consumed RP_DAT frames. |
-- The unit is also responsible for the identification of the FSS and FES fields of |
-- ID_DAT and RP_DAT frames and the verification of their CRC. |
-- At the end of a frame (FES detection) either the fss_crc_fes_ok_p_o pulse |
-- is assserted, indicating a frame with with correct FSS, CRC and FES |
-- or the pulse crc_wrong_p_o is asserted indicating an error on the CRC. |
-- If a FES is not detected after the reception of more than 8 bytes for an ID_DAT |
-- or more than 133 bytes for a RP_DAT the unit is reset by the wf_engine_control. |
-- The unit also remains reset during data production. |
-- |
-- Remark: We refer to |
-- o a significant edge : for the edge of a manch. encoded bit |
-- (bit 0: _|-, bit 1: -|_). |
-- |
-- o a transition : for the moment in between two adjacent bits, that|
-- may or may not result in an edge (eg. a 0 followed by a 0 will give an edge: |
-- _|-|_|-, but a 0 followed by a 1 will not: _|--|_ ). |
-- |
-- o the sampling of a manch. bit: for the moments when a manch. encoded bit should |
-- be sampled, before and after a significant edge. |
-- |
-- o the sampling of a bit : for the sampling of only the 1st part, |
-- before the transition. |
-- |
-- Example: |
-- bits : 0 1 |
-- manch. encoded : _|- -|_ |
-- significant edge : ^ ^ |
-- transition : ^ |
-- sample_manch_bit_p: ^ ^ ^ ^ |
-- sample_bit_p : ^ ^ (this sampling will give the 0 and the 1) |
-- |
-- |
-- Reminder of the consumed RP_DAT frame structure: |
-- _______ _______ ______ _______ ______ ________________ _______ ___________ _______ |
-- |__PRE__|__FSD__|_CTRL_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/02/2011 |
-- Version v0.05 |
-- Depends on wf_reset_unit |
-- wf_rx_osc |
-- wf_rx_deglitcher |
-- wf_engine_control |
---------------- |
-- Last changes |
-- 09/2009 v0.01 PAS First version |
-- 10/2010 v0.02 EG state switch_to_deglitched added; |
-- output signal rx_osc_rst_o added; signals renamed; |
-- state machine rewritten (moore style); |
-- units wf_rx_manch_code_check and Incoming_Bits_Index created; |
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES) |
-- code cleaned-up + commented. |
-- 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES; |
-- like this we confirm that the CRC_ok_p arrived just before the FES, |
-- and any 2 bytes that could by chanche be seen as CRC, are neglected. |
-- FSM data_field_byte state: redundant code removed: |
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then IDLE" |
-- code(more!)cleaned-up |
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if |
-- bytes with size different than 8 have preceeded. |
-- crc_wrong_p_o replaced the crc_wrong_p_o. |
-- 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state |
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with |
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1) |
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1); |
-- unit reset during production; |
-- check for code vilations completely removed! |
-- 10/2011 v0.05b EG moved session_timedout in the synchronous FSM process |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deserializer
--=================================================================================================
entity wf_rx_deserializer is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- by the engine_control (example: ID_DAT > 8 bytes,
-- RP_DAT > 133 bytes, wrong ID_DAT CTRL/ VAR/ SUBS bytes)
-- Signals from the wf_rx_deglitcher
fd_rxd_f_edge_p_i : in std_logic; -- indicates a falling edge on the deglitched FD_RXD
fd_rxd_r_edge_p_i : in std_logic; -- indicates a rising edge on the deglitched FD_RXD
fd_rxd_i : in std_logic; -- deglitched FD_RXD
-- Signals from the wf_rx_osc unit
sample_manch_bit_p_i : in std_logic; -- pulse indicating the sampling of a manch. bit
sample_bit_p_i : in std_logic; -- pulse indicating the sampling of a bit
signif_edge_window_i : in std_logic; -- time window where a significant edge is expected
adjac_bits_window_i : in std_logic; -- time window where a transition between adjacent
-- bits is expected
-- OUTPUTS
-- Signals to the wf_consumption and the wf_engine_control units
byte_o : out std_logic_vector (7 downto 0) ; -- retrieved data byte
byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES and CRC
-- Signal to the wf_production and the wf_engine_control units
crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with a
-- wrong CRC; pulse upon FES detection
-- Signal to the wf_engine_control unit
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
-- Signal to the wf_rx_osc unit
rx_osc_rst_o : out std_logic);-- resets the clk recovery procedure
end entity wf_rx_deserializer;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_deserializer is
-- FSM
type rx_st_t is (IDLE, PRE_FIELD_FIRST_F_EDGE, PRE_FIELD_R_EDGE, PRE_FIELD_F_EDGE, FSD_FIELD,
CTRL_DATA_FCS_FES_FIELDS);
signal rx_st, nx_rx_st : rx_st_t;
signal s_idle, s_receiving_pre, s_receiving_fsd, s_receiving_bytes : std_logic;
-- PRE detection
signal s_manch_r_edge_p, s_manch_f_edge_p, s_bit_r_edge_p, s_edge_out_manch_window_p : std_logic;
-- FSD, FES detection
signal s_fsd_bit, s_fsd_wrong_bit, s_fsd_last_bit, s_fes_detected : std_logic;
signal s_arriving_fes : std_logic_vector (15 downto 0);
-- bytes construction
signal s_write_bit_to_byte_p,s_byte_ready_p,s_byte_ready_p_d1,s_sample_manch_bit_p_d1: std_logic;
signal s_manch_bit_index_load_p, s_manch_bit_index_decr_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned (3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
-- CRC calculation
signal s_CRC_ok_p, s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
-- independent timeout counter
signal s_session_timedout : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deserializer's FSM --
---------------------------------------------------------------------------------------------------
-- Receiver's state machine: The state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Deserializer_FSM_Sync: storage of the current state of the FSM
-- A robust protection, that depends only on the system clock, has been implemented:
-- knowing that at any bit rate the reception of a frame should not last more than 35ms (this
-- corresponds to the consumption of 133 bytes at 31.25 Kbps), a counter has been implemented,
-- responsible for bringing the machine back to IDLE if more than 52ms (complete 21 bit counter)
-- have passed since the machine left the IDLE state.
Deserializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
rx_st <= IDLE;
else
rx_st <= nx_rx_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Deserializer_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_out_manch_window_p,
fd_rxd_f_edge_p_i, s_manch_r_edge_p, rx_st,
s_fsd_wrong_bit, s_manch_f_edge_p,
s_fsd_last_bit, s_fes_detected)
begin
case rx_st is
-- During the PRE, the wf_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the FD_RXD is taken into account. At this phase, the unit uses
-- the wf_rx_osc signals: adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to IDLE and the wf_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the wf_rx_osc signals: sample_manch_bit_p_i and sample_bit_p_i.
when IDLE =>
if fd_rxd_f_edge_p_i = '1' then -- falling edge detection
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
else
nx_rx_st <= IDLE;
end if;
when PRE_FIELD_FIRST_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch.
nx_rx_st <= PRE_FIELD_R_EDGE; -- rising edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
end if;
when PRE_FIELD_R_EDGE =>
if s_manch_f_edge_p = '1' then -- arrival of a manch. falling edge
nx_rx_st <= PRE_FIELD_F_EDGE; -- note: several loops between
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_R_EDGE;
end if;
when PRE_FIELD_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch. rising edge
nx_rx_st <= PRE_FIELD_R_EDGE;
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= FSD_FIELD; -- adjacent bits, signaling the
-- beginning of the 1st V+ violation
-- of the FSD
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_F_EDGE;
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- FD_RXD and it is comparing it to the nominal bit of the FSD; the signal s_fsd_wrong_bit
-- is doing this comparison. If a wrong bit is received, the state machine jumps back to IDLE,
-- whereas if the complete byte is correctly received, it jumps to the CTRL_DATA_FCS_FES_FIELDS.
when FSD_FIELD =>
if s_fsd_last_bit = '1' then -- reception of the last (15th)
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;-- FSD bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= IDLE;
else
nx_rx_st <= FSD_FIELD;
end if;
-- The state machine stays in the CTRL_DATA_FCS_FES_FIELDS state until a FES detection (or
-- a reset rx_rst_i signal or a s_session_timeout signal). In this state bytes are "blindly"
-- being constructed and it is the wf_engine_control unit that supervises what is being received;
-- if for example an ID_DAT is being received without a FES detected after 8 bytes or an
-- RP_DAT without a FES after 133 bytes, or if the CTRL byte of an ID_DAT is wrong, the
-- engine_control will discard the current reception and reset the FSM through the rx_rst_i.
when CTRL_DATA_FCS_FES_FIELDS =>
if s_fes_detected = '1' then
nx_rx_st <= IDLE;
else
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;
end if;
when OTHERS =>
nx_rx_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Deserializer_FSM_Comb_Output_Signals: Definition of the output
-- signals of the FSM
Deserializer_FSM_Comb_Output_Signals: process (rx_st)
begin
case rx_st is
when IDLE =>
------------------------------------
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when PRE_FIELD_FIRST_F_EDGE | PRE_FIELD_R_EDGE | PRE_FIELD_F_EDGE =>
s_idle <= '0';
------------------------------------
s_receiving_pre <= '1';
------------------------------------
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when FSD_FIELD =>
s_idle <= '0';
s_receiving_pre <= '0';
------------------------------------
s_receiving_fsd <= '1';
------------------------------------
s_receiving_bytes <= '0';
when CTRL_DATA_FCS_FES_FIELDS =>
s_idle <= '0';
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
------------------------------------
s_receiving_bytes <= '1';
------------------------------------
when OTHERS =>
------------------------------------
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Bytes Creation --
---------------------------------------------------------------------------------------------------
-- Synchronous process Append_Bit_To_Byte: Creation of bytes of data.
-- A new bit of the FD_RXD is appended to the output byte that is being formed when the FSM is in
-- the "CTRL_DATA_FCS_FES_FIELDS" state, on the "sample_bit_p_i" moments.
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte_ready_p_d1 <= '0';
s_sample_manch_bit_p_d1 <= '0';
s_byte <= (others => '0');
else
s_byte_ready_p_d1 <= s_byte_ready_p;
s_sample_manch_bit_p_d1 <= sample_manch_bit_p_i;
if s_write_bit_to_byte_p = '1' then
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte_p <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
and (not s_fes_detected);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a counter that manages the position of an incoming FD_RXD bit inside a manch.
-- encoded byte (16 bits).
Incoming_Bits_Index: wf_decr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load_p,
counter_decr_i => s_manch_bit_index_decr_p,
---------------------------------------------------
counter_o => s_manch_bit_index,
counter_is_zero_o => s_manch_bit_index_is_zero);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_bit_index_top <= to_unsigned (c_FSD'left-2, s_manch_bit_index_top'length) when s_receiving_pre = '1' else
to_unsigned (15, s_manch_bit_index_top'length) when s_receiving_bytes ='1' else
to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '1' when (s_idle ='1') else
s_manch_bit_index_is_zero and sample_manch_bit_p_i when (s_receiving_pre = '1') or (s_receiving_bytes = '1') else --reloading for every new byte
'0';
s_manch_bit_index_decr_p <= sample_manch_bit_p_i when (s_receiving_fsd = '1') or (s_receiving_bytes = '1') else '0';
---------------------------------------------------------------------------------------------------
-- FSD detection --
---------------------------------------------------------------------------------------------------
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
---------------------------------------------------------------------------------------------------
-- FES detection --
---------------------------------------------------------------------------------------------------
-- Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
-- manch. encoded bits received and the s_fes_detected indicates whether they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & fd_rxd_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected <= '1' when s_arriving_fes = c_FES else '0';
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the CRC calculator unit that verifies the received FCS field.
CRC_Verification : wf_crc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte_p,
data_bit_i => fd_rxd_i,
crc_o => open,
---------------------------------------------------
crc_ok_p_o => s_CRC_ok_p);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process that checks the position of the CRC bytes in the frame: The 1 uclk-
-- wide crc_ok_p coming from the CRC calculator is delayed for 1 complete byte. The matching of
-- this delayed pulse with the end of frame pulse (s_fes_detected), would confirm that the two
-- last bytes received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_receiving_bytes = '0' then
s_CRC_ok_p_d <= '0';
s_CRC_ok_p_found <= '0';
else
if s_CRC_ok_p = '1' then
s_CRC_ok_p_found <= '1';
end if;
if s_byte_ready_p = '1' and s_CRC_ok_p_found = '1' then -- arrival of the next byte
s_CRC_ok_p_d <= '1'; -- (FES normally)
s_CRC_ok_p_found <= '0';
else
s_CRC_ok_p_d <= '0';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to IDLE state, in case any other logic is being stuck. The length of the counter
-- is defined using the slowest bit rate and considering reception of the upper limit of 133 bytes.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments --
---------------------------------------------------------------------------------------------------
-- aux signals concurrent assignments :
s_manch_r_edge_p <= signif_edge_window_i and fd_rxd_r_edge_p_i;
s_manch_f_edge_p <= signif_edge_window_i and fd_rxd_f_edge_p_i;
s_bit_r_edge_p <= adjac_bits_window_i and fd_rxd_r_edge_p_i;
s_edge_out_manch_window_p <= (not signif_edge_window_i)and(fd_rxd_r_edge_p_i or fd_rxd_f_edge_p_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals concurrent assignments :
byte_o <= s_byte;
byte_ready_p_o <= s_byte_ready_p_d1;
rx_osc_rst_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
-- frame with correct FSS, CRC, FES (plus with number of bits multiple of 8)
fss_crc_fes_ok_p_o <= s_fes_detected and s_byte_ready_p_d1 and s_CRC_ok_p_d;
-- frame with wrong CRC; pulse upon FES detection
-- here the s_sample_manch_bit_p_d1 and not the s_byte_ready_p_d1 is used, so that frames
-- with number of bits not multiple of 8, but with correct FES, can be detected.
crc_wrong_p_o <= s_fes_detected and s_sample_manch_bit_p_d1 and (not s_CRC_ok_p_d);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE reception |
-- |
-- Even if the bit rate of the communication is known, jitter is expected to affect |
-- the arriving time of the incoming signal. The main idea of the unit is to |
-- recalculate the expected arrival time of the next incoming bit, based on the |
-- arrival of the previous one, so that drifts are not accumulated. The clock |
-- recovery is based on the Manchester 2 coding which ensures that there is one edge |
-- (transition) for each bit. |
-- |
-- In this unit, we refer to |
-- o a significant edge: for the edge of a manch. encoded bit (bit 0:_|-, bit 1: -|_)|
-- o a transition : for the moment in between two adjacent bits, that may or |
-- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-, |
-- but a 0 followed by a 1 will not _|--|_ ). |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
-- wf_deglitcher |
-- wf_rx_deserializer |
------------------ |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned; |
-- rx clk generation depends on edge detection;code cleanedup+commented |
-- rst_rx_osc signal clearified |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments |
-- 02/2011 v0.04 EG 2 units wf_rx_osc and wf_tx_osc; process replaced by wf_incr_counter |
-- check for code violations removed completely |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_osc
--=================================================================================================
entity wf_rx_osc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_deglitcher unit
fd_rxd_edge_p_i : in std_logic; -- indication of an edge on fd_rxd
-- Signal from wf_rx_deserializer unit
rx_osc_rst_i : in std_logic; -- resets the clock recovery procedure
-- OUTPUTS
-- Signals to the wf_rx_deserializer
rx_manch_clk_p_o : out std_logic; -- signal with uclk-wide pulses
-- o on a significant edge
-- o between adjacent bits
-- ____|-|___|-|___|-|___
rx_bit_clk_p_o : out std_logic; -- signal with uclk-wide pulses
-- o between adjacent bits
-- __________|-|_________
rx_signif_edge_window_o : out std_logic; -- time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic); -- time window where a transition between adjacent
-- bits is expected
end entity wf_rx_osc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_osc is
-- reception period counter
signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_period_c_reinit, s_period_c_is_full : std_logic;
-- windows formed, based on the counter
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
-- fd_rxd signal combined with the windows
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
-- clocks
signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Generation of windows where edges/ transitions are expected --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- # uclk ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
s_half_period <= s_period srl 1; -- 1/2 s_period
s_margin <= s_period srl 3; -- margin for jitter defined as 1/8 of the period
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter unit : the rx_counter starts counting after the
-- release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the
-- filtered FD_RXD; this edge should be representing the 1st Manchester 2 (manch.) encoded bit '1'
-- of the PREamble. Starting from this edge, other falling or rising significant edges, are
-- expected around one period (s_period) later. A time window around the expected arrival time is
-- set and its length is defined as 1/4th of the period (1/8th before and 1/8th after the expected
-- time). When the actual edge arrives, the counter is reset.
-- If that first falling edge of FD_RXD is finally proven not to belong to a valid PRE the counter
-- is reinitialialized through the rx_osc_rst_i signal from the wf_rx_deserializer.
rx_periods_count: wf_incr_counter
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_period_c_reinit,
counter_incr_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
------------------------------------------
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized: if nfip_rst_i is active or
-- if rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
or s_period_c_is_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments: creation of the windows where
-- "significant edges" and "adjacent bits transitions" are expected on the input signal.
-- o s_signif_edge_window: extends s_margin uclk ticks before and s_margin uclk ticks after
-- the completion of a period, where significant edges are expected.
-- o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after
-- the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_margin) or
(s_period_c > s_period-1 - s_margin-1)) else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and
(s_period_c < s_half_period+s_margin)) else '0';
---------------------------------------------------------------------------------------------------
-- Clocks Generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the fd_rxd
-- and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- The signal rx_manch_clk: is inverted on each significant edge, as well as between adjacent bits
-- The signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clks: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
s_manch_clk <= '0';
s_bit_clk <= '0';
s_bit_clk_d1 <= '0';
s_manch_clk_d1 <= '0';
s_signif_edge_found <= '0';
s_adjac_bits_edge_found <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before next cycle
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
-- s_manch_clk : ____|-----|_____|-----|____
-- s_manch_clk_d1 : ______|-----|_____|-----|__
-- rx_manch_clk_p_o : ____|-|___|-|___|-|___|-|__
s_bit_clk_d1 <= s_bit_clk;
-- s_bit_clk : ____|-----------|__________
-- s_bit_clk_d1 : ______|-----------|________
-- rx_bit_clk_p_o : ____|-|_________|-|________
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments --
---------------------------------------------------------------------------------------------------
rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after
-- o a significant edge and
-- o a new bit
-- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_bit_clk xor s_bit_clk_d1; -- a 1 uclk-wide pulse, after
-- o a new bit
-- _________|-|_________
rx_signif_edge_window_o <= s_signif_edge_window;
rx_adjac_bits_window_o <= s_adjac_bits_window;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_tx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_tx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE transmission. |
-- |
-- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit |
-- clock) and the nanoFIP internal signal tx_sched_p_buff: |
-- |
-- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-| |
-- FD_TXCK : _____|--------...--------|________...________|--------...--- |
-- tx_sched_p_buff(3): 0 0 0 1 0 0 0 1 |
-- tx_sched_p_buff(2): 0 0 1 0 0 0 1 0 |
-- tx_sched_p_buff(1): 0 1 0 0 0 1 0 0 |
-- tx_sched_p_buff(0): 1 0 0 0 1 0 0 0 |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; |
-- c_TX_SCHED_BUFF_LGTH got 1 bit more |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.04 EG wf_tx_osc as different unit; use of wf_incr_counter;added tx_osc_rst_p_i
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_tx_osc
--=================================================================================================
entity wf_tx_osc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_engine_control
tx_osc_rst_p_i : in std_logic; -- transmitter timeout
-- OUTPUTS
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; -- line driver half bit clock
-- Signal to the wf_tx_serializer unit
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-- buffer of pulses used for the scheduling
-- of the actions of the wf_tx_serializer
end entity wf_tx_osc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_tx_osc is
-- transmission periods counter
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_period_c_is_full, s_period_c_reinit : std_logic;
-- clocks
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_tx_sched_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Periods Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks for a
-- transmission period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter counting transmission periods.
tx_periods_count: wf_incr_counter
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_period_c_reinit,
counter_incr_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
---------------------------------------------------------------------------------------------------
-- Clocks Construction --
---------------------------------------------------------------------------------------------------
-- Concurrent signals assignments and a synchronous process that use
-- the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_sched_p_buff_o.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or
((s_period_c > (2*s_one_forth_period)-1) and
(s_period_c < 3*s_one_forth_period)))
else '0';
-- transm. period : _|-----------|___________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|-----|_____|-----|_____|--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Edge detector for s_tx_clk
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : _|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1: ___|-----|_____|-----|___
-- not s_tx_clk_d1 : ---|_____|-----|_____|---
-- s_tx_clk_p : _|-|___|-|___|-|___|-|___
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_sched_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
s_tx_clk_d1 <= s_tx_clk;
s_tx_sched_p_buff <= s_tx_sched_p_buff (s_tx_sched_p_buff'left-1 downto 0) & s_tx_clk_p;
-- buffering of the s_tx_clk_p pulses
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals
tx_clk_o <= s_tx_clk_d1;
tx_sched_p_buff_o <= s_tx_sched_p_buff;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_tx_serializer |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_tx_serializer.vhd |
-- |
-- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. |
-- It is retreiving bytes of data from: |
-- o the wf_production (from the CTRL byte until the MPS) |
-- o WF_PACKAGE (FSS and FES bytes) |
-- o and the wf_crc (FCS bytes). |
-- |
-- It encodes the bytes to the Manchester 2 (manch.)scheme and outputs one by one the|
-- encoded bits on the moments indicated by the wf_tx_osc unit. |
-- |
-- Reminder of the Produced RP_DAT frame structure : |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |------------- Bytes from the wf_production -------------| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2011 |
-- Version v0.05 |
-- Depends on wf_engine_control |
-- wf_production |
-- wf_tx_osc |
-- wf_reset_unit |
---------------- |
-- Last changes |
-- v0.02 2009 PAS Entity Ports added, start of architecture content |
-- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit |
-- briefly byte_index_i needed to arrive 1 clock tick earlier |
-- renamed from tx to tx_serializer; |
-- STOP_TRANSMISSION state added for the synch of txena |
-- v0.04 01/2011 EG SYNC_TO_TXCK state added to start always with the bits 1,2,3 of the |
-- clock buffer available(tx_start_p_i may arrive at any time) |
-- tx_completed_p_o signal added |
-- v0.05 07/2011 EG bits_to_txd unit removed |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_tx_serializer
--=================================================================================================
entity wf_tx_serializer is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_production
byte_i : in std_logic_vector (7 downto 0); -- byte to be delivered
-- Signals from the wf_engine_control unit
tx_start_p_i : in std_logic; -- indication for the start of the production
byte_request_accept_p_i : in std_logic; -- indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; -- indication of the last data byte
-- (CRC, FES not included)
-- Signal from the wf_tx_osc
tx_sched_p_buff_i : in std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
-- pulses for the transmission synchronization
-- OUTPUTS
-- Signal to the wf_engine_control unit
tx_byte_request_p_o : out std_logic; -- request for a new byte
tx_completed_p_o : out std_logic; -- pulse upon the end of transmission
-- Signal to the wf_tx_osc unit
tx_osc_rst_p_o : out std_logic; -- oscillator reset after a transmission error
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; -- transmitter serial data
tx_enable_o : out std_logic);-- transmitter enable
end entity wf_tx_serializer;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_tx_serializer is
-- FSM
type tx_st_t is (IDLE, SYNC_TO_TXCK, SEND_FSS, SEND_DATA_BYTE,
SEND_CRC_BYTES, SEND_FES, STOP_TRANSMISSION);
signal tx_st, nx_tx_st : tx_st_t;
signal s_prepare_to_produce, s_sending_fss, s_sending_data : std_logic;
signal s_sending_crc, s_sending_fes, s_stop_transmission : std_logic;
-- bits counter
signal s_bit_index_decr_p,s_bit_index_load, s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned (4 downto 0);
-- transmitter output
signal s_txd : std_logic;
-- byte to be transmitted
signal s_data_byte : std_logic_vector (7 downto 0);
signal s_data_byte_manch : std_logic_vector (15 downto 0);
-- CRC calculations
signal s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_crc_bytes : std_logic_vector (15 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
-- independent timeout counter
signal s_session_timedout : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- The signal tx_sched_p_buff_i is used for the scheduling of the state transitions of the machine
-- as well as of the actions on the output signals.
-- The following drawing shows the transitions of the signal tx_sched_p_buff_i with respect to
-- the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock).
-- FD_TXCK : _________|-------...---------|________...________|-------...---------|____
-- tx_sched_p_buff(3): |0|0|0|1 |0|0|0|1
-- tx_sched_p_buff(2): |0|0|1|0 |0|0|1|0
-- tx_sched_p_buff(1): |0|1|0|0 |0|1|0|0
-- tx_sched_p_buff(0): |1|0|0|0 |1|0|0|0
----------------------
-- new byte request : ^
-- new byte ready : . . ^
-- 1st bit of new . . . . . . . . . . . . . . . . . .^
-- byte delivery :
-- bit counter : [ 15 . . .][ 14
-- A new bit is delivered after the assertion of tx_sched_p_buff (1).
-- The counter Outgoing_Bits_Index that keeps the index of a bit being delivered is updated after
-- the delivery of the bit, after the tx_sched_p_buff (3) assertion. The counter is ahead of the
-- bit being sent.
-- In the sending_bytes state, where the unit is expecting data bytes from the wf_production,
-- the unit delivers a request for a new byte after the tx_sched_p_buff (0) assertion,
-- and when the Outgoing_Bits_Index counter is empty (which means that the last bit of a previous
-- byte is now being delivered).
-- The wf_engine_control responds to the request by sending a new address to the wf_production
-- for the retrieval of a byte from the memory or the stand-alone bus.
-- The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request,
-- and starts being transmitted at the tx_sched_p_buff (1) of the next FD_TXCK cycle.
-- The wf_engine_control is the one keeping track of the amount of bytes delivered and asserts
-- the last_byte_p_i signal accordingly; after the arrival of this signal the serializer's FSM
-- proceeds with the transmission of the CRC and the FES bytes and then goes back to IDLE.
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only
-- on the system clock, that from any state can bring the FSM back to IDLE. At any bit rate the
-- transmission of the longest RP_DAT should not last more than 35ms. Hence, we have generated a
-- 21 bits (c_SESSION_TIMEOUT_C_LGTH) counter that will reset the machine if more than 52ms
-- (complete 21 bit counter) have passed since it has left this IDLE state.
---------------------------------------------------------------------------------------------------
-- Serializer's FSM --
---------------------------------------------------------------------------------------------------
-- Serializer's state machine: the state machine is divided in three parts (a clocked
-- process to store the current state, a combinatorial process to manage state transitions and
-- finally a combinatorial process to manage the output signals), which are the 3 processes that
-- follow.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Serializer_FSM_Sync:
Serializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
tx_st <= IDLE;
else
tx_st <= nx_tx_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Serializer_FSM_Comb_State_Transitions
Serializer_FSM_Comb_State_Transitions: process (tx_st, tx_start_p_i, last_byte_p_i,
s_bit_index_is_zero, tx_sched_p_buff_i)
begin
case tx_st is
when IDLE =>
if tx_start_p_i = '1' then -- trigger from wf_engine_control
nx_tx_st <= SYNC_TO_TXCK;
else
nx_tx_st <= IDLE;
end if;
when SYNC_TO_TXCK => -- synch to the free running FD_TXTCK
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4) = '1' then
nx_tx_st <= SEND_FSS;
else
nx_tx_st <= SYNC_TO_TXCK;
end if;
when SEND_FSS => -- delivery of 2 FSS bytes
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) = '1') then
nx_tx_st <= SEND_DATA_BYTE;
else
nx_tx_st <= SEND_FSS;
end if;
when SEND_DATA_BYTE => -- delivery of several data bytes
-- until the last_byte_p_i notification
if last_byte_p_i = '1' then
nx_tx_st <= SEND_CRC_BYTES;
else
nx_tx_st <= SEND_DATA_BYTE;
end if;
when SEND_CRC_BYTES => -- delivery of 2 CRC bytes
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_st <= SEND_FES; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_sched_p_buff_i(3), to get the 31 as top value
else
nx_tx_st <= SEND_CRC_BYTES;
end if;
when SEND_FES => -- delivery of 1 FES byte
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_st <= STOP_TRANSMISSION; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_sched_p_buff_i(3) to get the 15 as top value
else
nx_tx_st <= SEND_FES;
end if;
when STOP_TRANSMISSION =>
-- end of transmission synchronous to the FD_TXCK
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then
nx_tx_st <= IDLE;
else
nx_tx_st <= STOP_TRANSMISSION;
end if;
when OTHERS =>
nx_tx_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Serializer_FSM_Comb_Output_Signals
Serializer_FSM_Comb_Output_Signals: process ( tx_st )
begin
case tx_st is
when IDLE | SYNC_TO_TXCK =>
---------------------------------
s_prepare_to_produce <= '1';
---------------------------------
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
when SEND_FSS =>
s_prepare_to_produce <= '0';
---------------------------------
s_sending_fss <= '1';
---------------------------------
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
when SEND_DATA_BYTE =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
---------------------------------
s_sending_data <= '1';
---------------------------------
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
when SEND_CRC_BYTES =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
---------------------------------
s_sending_crc <= '1';
---------------------------------
s_sending_fes <= '0';
s_stop_transmission <= '0';
when SEND_FES =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
---------------------------------
s_sending_fes <= '1';
---------------------------------
s_stop_transmission <= '0';
when STOP_TRANSMISSION =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
---------------------------------
s_stop_transmission <= '1';
---------------------------------
when OTHERS =>
---------------------------------
s_prepare_to_produce <= '1';
---------------------------------
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Input Byte Retrieval --
---------------------------------------------------------------------------------------------------
Input_Byte_Retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_data_byte <= (others => '0');
else
if byte_request_accept_p_i = '1' then
s_data_byte <= byte_i;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Manchester Encoding --
---------------------------------------------------------------------------------------------------
s_data_byte_manch <= f_manch_encoder (s_data_byte);
s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes);
---------------------------------------------------------------------------------------------------
-- CRC calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the CRC unit
crc_generation: wf_crc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_ok_p_o => open,
-------------------------------------------------
crc_o => s_crc_bytes);
-------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
s_start_crc_p <= s_sending_fss and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
-- the CRC calculation starts when at the end of th e FSS (beginning of data bytes delivery)
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
---------------------------------------------------------------------------------------------------
-- Bits counter --
---------------------------------------------------------------------------------------------------
-- Managment of the pointer that indicates which bit of a manchester encoded byte is to be
-- delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a
-- CRC or a FES byte.
Outgoing_Bits_Index: wf_decr_counter
generic map(g_counter_lgth => 5)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_i => s_bit_index_decr_p,
-----------------------------------------------
counter_o => s_bit_index,
counter_is_zero_o => s_bit_index_is_zero);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_bit_index_top <= to_unsigned (15, s_bit_index'length) when s_sending_fss = '1' or s_sending_data = '1' else
to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length) when s_sending_crc = '1' else
to_unsigned (c_FES'length - 1, s_bit_index'length) when s_sending_fes = '1' else
to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= (s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1)) when
(s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else
'1' when s_prepare_to_produce ='1' else
'0';
s_bit_index_decr_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) when
(s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '0';
---------------------------------------------------------------------------------------------------
-- Bits delivery --
---------------------------------------------------------------------------------------------------
-- Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by
-- placing bits of data according to the state of wf_tx_serializer's state machine and to the
-- counter s_bit_index. The delivery takes place upon a tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3)
-- pulse.
Bits_Delivery: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_txd <= '0';
else
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then
if s_sending_fss = '1' then
s_txd <= c_FSS (to_integer (s_bit_index)); -- FSS: 2 bytes long (no need to resize)
elsif s_sending_data = '1' then
s_txd <= s_data_byte_manch (to_integer (resize(s_bit_index, 4))); -- 1 data-byte at a time
elsif s_sending_crc = '1' then
s_txd <= s_crc_bytes_manch (to_integer (s_bit_index)); -- CRC: 2 bytes long
elsif s_sending_fes = '1' then
s_txd <= c_FES(to_integer (resize(s_bit_index,4))); -- FES: 1 byte
else
s_txd <= '0';
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- TXENA generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
-- same moment as the first bit of the FSS starts being delivered and stays asserted until the
-- end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_enable_o <= '0';
else
if ((s_sending_fss = '1') or (s_sending_data = '1') or (s_sending_crc = '1') or
(s_sending_fes = '1') or (s_stop_transmission = '1')) then -- tx sending bits
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then
-- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enable with the
-- the delivery of the 1st FSS bit
end if; -- FD_TXD (FSS) :________|-----|___________|--------
-- tx_sched_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- FD_TXENA :________|--------------------------
else
tx_enable_o <= '0';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter relying only on the system clock as an additional
-- way to go back to IDLE state, in case any other logic is being stuck.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_prepare_to_produce,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
tx_data_o <= s_txd;
tx_osc_rst_p_o <= s_session_timedout;
tx_completed_p_o <= s_stop_transmission and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2);
tx_byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4);
-- request for a new byte from the wf_prod_bytes_retriever unit (passing from wf_engine_control)
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ 3c5faced
......@@ -62,7 +62,11 @@ architecture behavioral of tb_masterFIP is
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
ext_sync_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
......@@ -520,7 +524,7 @@ begin
nostat_i => nostat,
rstin_i => (rst_n),--was not
rstpon_i => '1',
slone_i => '0',
slone_i => '0', --slone,
rston_o => urst_from_nf,
var1_acc_i => var1_acc,
......
syn/spec/spec_masterfip.xise
View file @ 3c5faced
......@@ -16,11 +16,11 @@
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
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......@@ -28,7 +28,7 @@
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......@@ -60,7 +60,7 @@
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......@@ -76,7 +76,7 @@
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......@@ -112,7 +112,7 @@
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......@@ -120,43 +120,43 @@
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......@@ -180,19 +180,19 @@
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......@@ -232,7 +232,7 @@
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......@@ -300,7 +300,7 @@
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......@@ -308,7 +308,7 @@
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......@@ -316,11 +316,11 @@
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......@@ -328,7 +328,7 @@
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......@@ -344,7 +344,7 @@
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......@@ -480,7 +480,7 @@
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......@@ -628,23 +628,23 @@
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......@@ -652,15 +652,15 @@
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......@@ -670,19 +670,19 @@
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......@@ -694,79 +694,79 @@
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......@@ -793,7 +793,7 @@
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......@@ -809,47 +809,47 @@
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......@@ -902,7 +902,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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......@@ -910,142 +910,143 @@
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<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
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<library xil_pn:name="nanoFIP_lib"/>
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<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
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<library xil_pn:name="nanoFIP_lib"/>
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<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="325"/>
<library xil_pn:name="nanoFIP_lib"/>
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<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1420,7 +1421,6 @@
</bindings>
<libraries>
<library xil_pn:name="nanoFIP"/>
<library xil_pn:name="nanoFIP_lib"/>
</libraries>
......
syn/spec/tb_masterFIP.fdo 0 → 100644
View file @ 3c5faced
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Tue Mar 15 09:49:08 W. Europe Standard Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
## ---------------------DO NOT EDIT THIS FILE-------------------------
## You may want to add additional commands to control the simulation
## in the user specific do file (<module>.udo) which is automatically
## generated in the project directory and will not be removed on
## subsequent simulation flows run from Project Navigator.
## ---------------------DO NOT EDIT THIS FILE-------------------------
##
######################################################################
#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_package.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_incr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_decr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_crc.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_crc.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/util.vhd"
vcom -explicit -93 "../../rtl/masterFIP_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_tx_serializer.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_tx_osc.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_osc.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_deserializer.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_deglitcher.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
vlog "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/masterfip_tx.vhd"
vcom -explicit -93 "../../rtl/masterfip_rx.vhd"
vcom -explicit -93 "../../rtl/incr_counter.vhd"
vcom -explicit -93 "../../rtl/fmc_masterfip_csr.vhd"
vcom -explicit -93 "../../rtl/decr_counter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../top/spec/synthesis_descriptor.vhd"
vcom -explicit -93 "../../top/spec/spec_reset_gen.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_config.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_access_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_interface.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/mem_model.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../rtl/carrier_info.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../top/spec/spec_masterFIP.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/nanofip.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router.vhd"
vcom -explicit -93 "../../sim/spec/testbench/board_settings.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_masterFIP.vhd"
vlog "C:/EDA/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.tb_masterFIP glbl
#
# Source the wave do file
#
do {tb_masterFIP_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {tb_masterFIP.udo}
#
# Run simulation for this time
#
run 1000ns
#
# End
#
syn/spec_mt/spec_masterfip_mt.xise
View file @ 3c5faced
......@@ -627,7 +627,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
......@@ -936,7 +936,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1062,7 +1062,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1306,7 +1306,7 @@
</file>
<file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../top/spec_mt/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
......
top/spec/spec_masterfip.vhd
View file @ 3c5faced
......@@ -169,6 +169,10 @@ entity spec_masterfip is
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0); -- DAC configuration (so that the MT-generated
dac_sclk_o : out std_logic; -- 100 MHz clk has its max stability)
dac_din_o : out std_logic;
led_tx_err_n_o : out std_logic; -- LEDs mezzanine front pannel
led_tx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
......
top/spec_mt/spec_masterfip_mt.ucf
View file @ 3c5faced
......@@ -157,6 +157,17 @@ NET "FMC_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FMC_SDA_B" LOC = F8;
NET "FMC_SDA_B" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 3c5faced
......@@ -92,11 +92,11 @@ entity spec_masterfip_mt is
led_red : out std_logic;
led_green : out std_logic;
-- SPEC EEPROM
-- SPEC EEPROM (driven by the MT core)
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
-- SPEC 1-wire
-- SPEC 1-wire (driven by the MT core)
carrier_onewire_b : inout std_logic;
fmc_prsnt_m2c_l_i : in std_logic;
......@@ -128,6 +128,11 @@ entity spec_masterfip_mt is
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- DAC configuration (so that the MT-generated 100 MHz clk has its max stability)
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
-- WorldFIP LEDs
led_tx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
......@@ -325,6 +330,10 @@ begin
adc_5v_en_n_o => adc_5v_en_n_o,
adc_prim_conn_n_o => adc_prim_conn_n_o,
adc_sec_conn_n_o => adc_sec_conn_n_o,
-- DAC configuration
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
-- WISHBONE interface with
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
......@@ -338,10 +347,10 @@ begin
-- Aux
aux_o => aux);
-----------------------------------------------------
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
fd_txena_o <= fd_txena;
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
fd_txena_o <= fd_txena;
---------------------------------------------------------------------------------------------------
......
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