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MasterFIP - Gateware
Commit 2b615c20 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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WIP: added 2 more rx status bits: one activated upon CTRL byte reception and one… 

WIP: added 2 more rx status bits: one activated upon CTRL byte reception and one upon detection of more bytes than the max frame size
parent 0c53da28
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Showing with 1144 additions and 55995 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 2b615c20
......@@ -440,7 +440,6 @@ begin
-- counter counting the turnaround time i.e. the time after the end of transmission of a frame
-- (tx_completed_p), or after the end of reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p)
-- and before the transmission of a new frame.
-- Note that the MT is using the turnar_cnt rather than the 1-clk-tick long counter_is_zero pulse
-- turnaround counter
cmp_turnaround_cnt: decr_counter
......@@ -451,7 +450,7 @@ begin
counter_load_i => turnar_load_p,
counter_top_i => reg_from_mt.turnar_lgth_o,
counter_o => reg_to_mt.turnar_time_cnt_i,
counter_is_zero_o => open);
counter_is_zero_o => open); -- too fast to be used by MT
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.turnar_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
......@@ -473,7 +472,7 @@ begin
counter_load_i => silen_load_p,
counter_top_i => reg_from_mt.silen_lgth_o,
counter_o => reg_to_mt.silen_time_cnt_i,
counter_is_zero_o => open);
counter_is_zero_o => open); -- too fast to be used by MT
-- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.silen_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
......@@ -493,10 +492,12 @@ begin
rx_byte_index_o => rx_byte_index, -- current byte index
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i(C_FRAME_WORDS_CNT_LGTH-1 downto 0),
rx_ctrl_byte_o => reg_to_mt.rx_payld_ctrl_i,
rx_ctrl_byte_ok_o => reg_to_mt.rx_stat_ctrl_byte_ok_i,
rx_frame_o => rx_frame,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
rx_fss_received_p_o => rx_fss_received_p,
rx_crc_wrong_p_o => rx_crc_wrong_p,
rx_bytes_num_err_o => reg_to_mt.rx_stat_bytes_num_err_i,
rx_byte_o => rx_byte, -- for debugging
rx_byte_ready_p_o => rx_byte_ready_p);-- for debugging
......
rtl/masterFIP_pkg.vhd
View file @ 2b615c20
......@@ -59,8 +59,8 @@ package masterFIP_pkg is
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
constant C_BYTE_WIDTH : integer := 8;
constant C_WORD_WIDTH : integer := 32;
constant C_BYTE_WIDTH : integer := 8; -- 8-bit bytes
constant C_WORD_WIDTH : integer := 32; -- 32-bit words
-- Declaration of a structure with 67 words of 32-bit each = 268 bytes which represent the max
-- length of a frame, including
......@@ -74,15 +74,23 @@ package masterFIP_pkg is
-- until the FES detection; therefore the max amount of bytes expected to be counted by the
-- deserializer is 266. Upon the rx_fss_crc_fes_ok_p_o the processor needs to read the rx_ctrl_byte
-- (separate register, not included in the rx_frame structure) and rx_byte_index_o-4 bytes from the
-- rx_frame structure (minus the CTRL, CRC and FES bytes).
-- rx_frame structure (minus the CTRL, 2x CRC and FES bytes).
-- Note that the serializer, is counting one by one the bytes that are serialized, after the FSS and
-- before the CRC; therefore the max amount of bytes expected to be counted by the serializer is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 67;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- ((std_logic_vector(C_MAX_FRAME_WORDS))'left)
constant C_FRAME_BYTES_CNT_LGTH : integer := 9; -- (((std_logic_vector(C_MAX_FRAME_WORDS) srl 2))'left)
constant C_MAX_FRAME_BYTES : integer := 266;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 67 words; for normal tx operation it should
-- not exceed 66 words
constant C_FRAME_BYTES_CNT_LGTH : integer := 9; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 266 bytes; for normal tx operation it should
-- not exceed 263 bytes
subtype data_word is std_logic_vector(C_WORD_WIDTH-1 downto 0);
......@@ -177,12 +185,14 @@ package masterFIP_pkg is
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_ctrl_byte_ok_o : out std_logic;
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
rx_crc_wrong_p_o : out std_logic;
rx_bytes_num_err_o : out std_logic);
end component masterfip_rx;
......
rtl/masterfip_rx.vhd
View file @ 2b615c20
......@@ -139,6 +139,9 @@ entity masterfip_rx is port(
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0); -- frame CTRL byte
rx_ctrl_byte_ok_o : out std_logic; -- active after the reception of the CTRL byte (first
-- byte after FSS) and until a rst_i OR rst_rx_i
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 67 words of 32-bit each = 268 bytes
-- able to house a frame of max length.
......@@ -153,7 +156,10 @@ entity masterfip_rx is port(
rx_crc_wrong_p_o : out std_logic; -- indication of a frame with wrong CRC; pulse upon FES
rx_fss_received_p_o : out std_logic); -- pulse upon FSS detection (ID/ RP_DAT)
rx_fss_received_p_o : out std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MAX_FRAME_BYTES bytes
-- and until a rst_i OR rst_rx_i
end entity masterfip_rx;
......@@ -264,27 +270,49 @@ begin
rx_byte_index_o <= rx_byte_index;
---------------------------------------------------------------------------------------------------
-- rx bytes exceeded C_MAX_FRAME_BYTES --
---------------------------------------------------------------------------------------------------
-- indication that the rx counter exceeded the max expected number of bytes
p_rx_bytes_num_err: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_bytes_num_err_o <= '0';
else
if unsigned(rx_byte_index) > C_MAX_FRAME_BYTES then
rx_bytes_num_err_o <= '1';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
-- note: the values of the CTRL byte and all payload regs are kept till a rx_rst_i or a rst_i
p_create_32bit_words: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
byte0 <= (others => '0');
byte1 <= (others => '0');
byte2 <= (others => '0');
byte3 <= (others => '0');
rx_ctrl_byte_o <= (others => '0');
else
byte0 <= (others => '0');
byte1 <= (others => '0');
byte2 <= (others => '0');
byte3 <= (others => '0');
rx_ctrl_byte_o <= (others => '0');
rx_ctrl_byte_ok_o <= '0';
else
if rx_byte_ready_p = '1' then
if unsigned(rx_byte_index) = resize(unsigned(c_CTRL_BYTE_INDEX),C_FRAME_BYTES_CNT_LGTH) then
rx_ctrl_byte_o <= rx_byte;
rx_ctrl_byte_o <= rx_byte; -- CTRL byte stored in separate word from the rest of the frame
rx_ctrl_byte_ok_o <= '1'; -- value kept till a rst
else
byte0 <= rx_byte;
byte1 <= byte0;
byte2 <= byte1;
byte3 <= byte2;
byte0 <= rx_byte;
byte1 <= byte0;
byte2 <= byte1;
byte3 <= byte2;
end if;
end if;
end if;
......@@ -340,8 +368,14 @@ begin
end if; -- Note: for [CRC|BYTE|BYTE|BYTE], upon
-- rx_fss_crc_fes_ok_p a new word has been created
elsif (rx_byte_ready_p = '1' and unsigned(rx_byte_index_d1) > 0 and unsigned(rx_byte_index_d1) mod 4 = 0) then
-- for the rest of the bytes, i.e. everything before the rx_fss_crc_fes_ok_p, a new word is
-- created after the reception of 4 bytes.
-- note that rx_byte_index is checked to be within the limits [1..262], as:
-- rx_byte_index = 0 refers to the CTRL byte that is written in a separate word, and
-- when rx_byte_index = 262: the one-but-last word (rx_frame_o(66)) of a max-length-frame
-- is written; the last word (rx_frame_o(67)) of a max-length-frame will be written
-- upon rx_fss_crc_fes_ok_p.
elsif (rx_byte_ready_p = '1' and unsigned(rx_byte_index_d1) > 0 and unsigned(rx_byte_index_d1) < 263 and unsigned(rx_byte_index_d1) mod 4 = 0) then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if;
......
rtl/masterfip_wbgen2_csr.vhd
View file @ 2b615c20
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 06/30/17 14:35:27
-- Version : 0x00010000
-- Created : 07/14/17 20:28:20
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -157,7 +157,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000010000000000000000";
masterfip_ver_id_int <= "00000000000000100000000000000000";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
......@@ -663,11 +663,11 @@ begin
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.rx_stat_pream_ok_i;
rddata_reg(1) <= regs_i.rx_stat_frame_ok_i;
rddata_reg(2) <= regs_i.rx_stat_frame_crc_err_i;
rddata_reg(1) <= regs_i.rx_stat_ctrl_byte_ok_i;
rddata_reg(2) <= regs_i.rx_stat_frame_ok_i;
rddata_reg(3) <= regs_i.rx_stat_frame_crc_err_i;
rddata_reg(4) <= regs_i.rx_stat_bytes_num_err_i;
rddata_reg(23 downto 8) <= regs_i.rx_stat_bytes_num_i;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -1820,8 +1820,10 @@ begin
-- rx Preamble(FSS) detected
-- rx CTRL byte detected
-- rx frame ok
-- rx frame crc error
-- rx bytes number error
-- rx number of payload bytes
-- current word index
-- rx number of frames with CRC error
......
rtl/masterfip_wbgen2_pkg.vhd
View file @ 2b615c20
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 06/30/17 14:35:27
-- Version : 0x00010000
-- Created : 07/14/17 20:28:20
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -39,8 +39,10 @@ package masterfip_wbgen2_pkg is
fd_txer_cnt_i : std_logic_vector(31 downto 0);
fd_txer_tstamp_i : std_logic_vector(31 downto 0);
rx_stat_pream_ok_i : std_logic;
rx_stat_ctrl_byte_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(7 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
......@@ -133,8 +135,10 @@ package masterfip_wbgen2_pkg is
fd_txer_cnt_i => (others => '0'),
fd_txer_tstamp_i => (others => '0'),
rx_stat_pream_ok_i => '0',
rx_stat_ctrl_byte_ok_i => '0',
rx_stat_frame_ok_i => '0',
rx_stat_frame_crc_err_i => '0',
rx_stat_bytes_num_err_i => '0',
rx_stat_bytes_num_i => (others => '0'),
rx_stat_curr_word_indx_i => (others => '0'),
rx_stat_crc_err_cnt_i => (others => '0'),
......@@ -450,8 +454,10 @@ tmp.fd_wdg_tstamp_i := f_x_to_zero(left.fd_wdg_tstamp_i) or f_x_to_zero(right.fd
tmp.fd_txer_cnt_i := f_x_to_zero(left.fd_txer_cnt_i) or f_x_to_zero(right.fd_txer_cnt_i);
tmp.fd_txer_tstamp_i := f_x_to_zero(left.fd_txer_tstamp_i) or f_x_to_zero(right.fd_txer_tstamp_i);
tmp.rx_stat_pream_ok_i := f_x_to_zero(left.rx_stat_pream_ok_i) or f_x_to_zero(right.rx_stat_pream_ok_i);
tmp.rx_stat_ctrl_byte_ok_i := f_x_to_zero(left.rx_stat_ctrl_byte_ok_i) or f_x_to_zero(right.rx_stat_ctrl_byte_ok_i);
tmp.rx_stat_frame_ok_i := f_x_to_zero(left.rx_stat_frame_ok_i) or f_x_to_zero(right.rx_stat_frame_ok_i);
tmp.rx_stat_frame_crc_err_i := f_x_to_zero(left.rx_stat_frame_crc_err_i) or f_x_to_zero(right.rx_stat_frame_crc_err_i);
tmp.rx_stat_bytes_num_err_i := f_x_to_zero(left.rx_stat_bytes_num_err_i) or f_x_to_zero(right.rx_stat_bytes_num_err_i);
tmp.rx_stat_bytes_num_i := f_x_to_zero(left.rx_stat_bytes_num_i) or f_x_to_zero(right.rx_stat_bytes_num_i);
tmp.rx_stat_curr_word_indx_i := f_x_to_zero(left.rx_stat_curr_word_indx_i) or f_x_to_zero(right.rx_stat_curr_word_indx_i);
tmp.rx_stat_crc_err_cnt_i := f_x_to_zero(left.rx_stat_crc_err_cnt_i) or f_x_to_zero(right.rx_stat_crc_err_cnt_i);
......
rtl/wbgen/build_from_wb.sh
View file @ 2b615c20
......@@ -3,7 +3,7 @@
wbgen2 -V masterfip_wbgen2_csr.vhd -H record -p masterfip_wbgen2_pkg.vhd -s defines -C masterfip_wbgen2_csr.h -D masterfip_wbgen2_csr.html masterfip_csr.wb
echo ""
echo "Moving WB generated files to the following locations..."
echo "Moving wbgen2 generated files to the following locations..."
echo ""
mv -v ./master_wbgen2_csr.vhd ../.
......
rtl/wbgen/masterfip_csr.wb
View file @ 2b615c20
......@@ -3,7 +3,7 @@ peripheral {
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "masterfip_wbgen2_csr";
prefix = "masterfip";
version = 1;
version = 0x020000; -- major: 02 minor: 00 micro: 00
-- Note that for html readability, some of the lines are longer than 100 characters.
......@@ -632,6 +632,19 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "rx CTRL byte detected";
description = "indication that the deserializer has received the CTRL byte, i.e. the first byte after a Preamble(FSS);\
the bit stays active until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).\
Note that the content of the byte is not checked against acceptable CTRL byte codes";
prefix = "ctrl_byte_ok";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx frame ok";
description = "indication that the deserializer has finished with the reception of a complete frame;\
......@@ -656,6 +669,17 @@ peripheral {
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx bytes number error";
description = "indication that the deserializer has counted the reception of more than 266 bytes;\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "bytes_num_err";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......
rtl/wbgen/masterfip_wbgen2_csr.h deleted 100644 → 0
View file @ 0c53da28
/*
Register definitions for slave core: FMC masterFIP core registers
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 06/30/17 14:35:28
* Version : 0x00010000
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* version definition */
#define WBGEN2_MASTERFIP_VERSION 0x00010000
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define MASTERFIP_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define MASTERFIP_VER_ID_SHIFT 0
#define MASTERFIP_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MASTERFIP_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: rst */
/* definitions for field: reset of the masterFIP core in reg: rst */
#define MASTERFIP_RST_CORE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: reset of the FielDrive chip in reg: rst */
#define MASTERFIP_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: core id */
/* definitions for register: leds and debug */
/* definitions for field: rx act green led in reg: leds and debug */
#define MASTERFIP_LED_RX_ACT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx err red led in reg: leds and debug */
#define MASTERFIP_LED_RX_ERR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx act green led in reg: leds and debug */
#define MASTERFIP_LED_TX_ACT WBGEN2_GEN_MASK(2, 1)
/* definitions for field: tx err red led in reg: leds and debug */
#define MASTERFIP_LED_TX_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: ext sync act green led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync err red led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(5, 1)
/* definitions for field: dbg in reg: leds and debug */
#define MASTERFIP_LED_DBG_MASK WBGEN2_GEN_MASK(8, 24)
#define MASTERFIP_LED_DBG_SHIFT 8
#define MASTERFIP_LED_DBG_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define MASTERFIP_LED_DBG_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: fmc temperature */
/* definitions for register: fmc unique id lsb */
/* definitions for register: fmc unique id msb */
/* definitions for register: ext sync ctrl */
/* definitions for field: termination enable in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: transceiver direction in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: transceiver output enable negative logic in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OE_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: pulses counter reset in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: counting options in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OPT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: safe window in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_SAFE_WIND WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ext sync pulses cnt */
/* definitions for register: bus speed */
/* definitions for register: macrocycle lgth */
/* definitions for field: macrocycle lgth in reg: macrocycle lgth */
#define MASTERFIP_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_MACROCYC_LGTH_SHIFT 0
#define MASTERFIP_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: macrocycle cnt start in reg: macrocycle lgth */
#define MASTERFIP_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: macrocycle time cnt */
/* definitions for register: macrocycles number cnt */
/* definitions for register: turnaround lgth */
/* definitions for field: turnaround time in reg: turnaround lgth */
#define MASTERFIP_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_TURNAR_LGTH_SHIFT 0
#define MASTERFIP_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: turnaround cnt start in reg: turnaround lgth */
#define MASTERFIP_TURNAR_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: turnaround time cnt */
/* definitions for register: silence lgth */
/* definitions for field: silence time in reg: silence lgth */
#define MASTERFIP_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_SILEN_LGTH_SHIFT 0
#define MASTERFIP_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: silence cnt start in reg: silence lgth */
#define MASTERFIP_SILEN_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: silence time cnt */
/* definitions for register: tx ctrl */
/* definitions for field: tx rst in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx strt in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MASTERFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: tx status */
/* definitions for field: tx ended in reg: tx status */
#define MASTERFIP_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx enable in reg: tx status */
#define MASTERFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 16
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FielDrive wdgn, cdn */
/* definitions for field: FielDrive watchdog in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_WDG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FielDrive carrier detect in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_CD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: FielDrive wdg timestamp */
/* definitions for register: FielDrive txer cnt */
/* definitions for register: FielDrive txer tstamp */
/* definitions for register: rx ctrl */
/* definitions for field: rx rst in reg: rx ctrl */
#define MASTERFIP_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: rx status */
/* definitions for field: rx Preamble(FSS) detected in reg: rx status */
#define MASTERFIP_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx frame ok in reg: rx status */
#define MASTERFIP_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: rx frame crc error in reg: rx status */
#define MASTERFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx number of payload bytes in reg: rx status */
#define MASTERFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MASTERFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: rx current word index */
/* definitions for register: rx num of frames with CRC error */
/* definitions for register: rx payload ctrl byte */
/* definitions for register: rx payload reg1 */
/* definitions for register: rx payload reg2 */
/* definitions for register: rx payload reg3 */
/* definitions for register: rx payload reg4 */
/* definitions for register: rx payload reg5 */
/* definitions for register: rx payload reg6 */
/* definitions for register: rx payload reg7 */
/* definitions for register: rx payload reg8 */
/* definitions for register: rx payload reg9 */
/* definitions for register: rx payload reg10 */
/* definitions for register: rx payload reg11 */
/* definitions for register: rx payload reg12 */
/* definitions for register: rx payload reg13 */
/* definitions for register: rx payload reg14 */
/* definitions for register: rx payload reg15 */
/* definitions for register: rx payload reg16 */
/* definitions for register: rx payload reg17 */
/* definitions for register: rx payload reg18 */
/* definitions for register: rx payload reg19 */
/* definitions for register: rx payload reg20 */
/* definitions for register: rx payload reg21 */
/* definitions for register: rx payload reg22 */
/* definitions for register: rx payload reg23 */
/* definitions for register: rx payload reg24 */
/* definitions for register: rx payload reg25 */
/* definitions for register: rx payload reg26 */
/* definitions for register: rx payload reg27 */
/* definitions for register: rx payload reg28 */
/* definitions for register: rx payload reg29 */
/* definitions for register: rx payload reg30 */
/* definitions for register: rx payload reg31 */
/* definitions for register: rx payload reg32 */
/* definitions for register: rx payload reg33 */
/* definitions for register: rx payload reg34 */
/* definitions for register: rx payload reg35 */
/* definitions for register: rx payload reg36 */
/* definitions for register: rx payload reg37 */
/* definitions for register: rx payload reg38 */
/* definitions for register: rx payload reg39 */
/* definitions for register: rx payload reg40 */
/* definitions for register: rx payload reg41 */
/* definitions for register: rx payload reg42 */
/* definitions for register: rx payload reg43 */
/* definitions for register: rx payload reg44 */
/* definitions for register: rx payload reg45 */
/* definitions for register: rx payload reg46 */
/* definitions for register: rx payload reg47 */
/* definitions for register: rx payload reg48 */
/* definitions for register: rx payload reg49 */
/* definitions for register: rx payload reg50 */
/* definitions for register: rx payload reg51 */
/* definitions for register: rx payload reg52 */
/* definitions for register: rx payload reg53 */
/* definitions for register: rx payload reg54 */
/* definitions for register: rx payload reg55 */
/* definitions for register: rx payload reg56 */
/* definitions for register: rx payload reg57 */
/* definitions for register: rx payload reg58 */
/* definitions for register: rx payload reg59 */
/* definitions for register: rx payload reg60 */
/* definitions for register: rx payload reg61 */
/* definitions for register: rx payload reg62 */
/* definitions for register: rx payload reg63 */
/* definitions for register: rx payload reg64 */
/* definitions for register: rx payload reg65 */
/* definitions for register: rx payload reg66 */
/* definitions for register: rx payload reg67 */
/* definitions for register: tx ctrl byte */
/* definitions for register: tx payload reg1 */
/* definitions for register: tx payload reg2 */
/* definitions for register: tx payload reg3 */
/* definitions for register: tx payload reg4 */
/* definitions for register: tx payload reg5 */
/* definitions for register: tx payload reg6 */
/* definitions for register: tx payload reg7 */
/* definitions for register: tx payload reg8 */
/* definitions for register: tx payload reg9 */
/* definitions for register: tx payload reg10 */
/* definitions for register: tx payload reg11 */
/* definitions for register: tx payload reg12 */
/* definitions for register: tx payload reg13 */
/* definitions for register: tx payload reg14 */
/* definitions for register: tx payload reg15 */
/* definitions for register: tx payload reg16 */
/* definitions for register: tx payload reg17 */
/* definitions for register: tx payload reg18 */
/* definitions for register: tx payload reg19 */
/* definitions for register: tx payload reg20 */
/* definitions for register: tx payload reg21 */
/* definitions for register: tx payload reg22 */
/* definitions for register: tx payload reg23 */
/* definitions for register: tx payload reg24 */
/* definitions for register: tx payload reg25 */
/* definitions for register: tx payload reg26 */
/* definitions for register: tx payload reg27 */
/* definitions for register: tx payload reg28 */
/* definitions for register: tx payload reg29 */
/* definitions for register: tx payload reg30 */
/* definitions for register: tx payload reg31 */
/* definitions for register: tx payload reg32 */
/* definitions for register: tx payload reg33 */
/* definitions for register: tx payload reg34 */
/* definitions for register: tx payload reg35 */
/* definitions for register: tx payload reg36 */
/* definitions for register: tx payload reg37 */
/* definitions for register: tx payload reg38 */
/* definitions for register: tx payload reg39 */
/* definitions for register: tx payload reg40 */
/* definitions for register: tx payload reg41 */
/* definitions for register: tx payload reg42 */
/* definitions for register: tx payload reg43 */
/* definitions for register: tx payload reg44 */
/* definitions for register: tx payload reg45 */
/* definitions for register: tx payload reg46 */
/* definitions for register: tx payload reg47 */
/* definitions for register: tx payload reg48 */
/* definitions for register: tx payload reg49 */
/* definitions for register: tx payload reg50 */
/* definitions for register: tx payload reg51 */
/* definitions for register: tx payload reg52 */
/* definitions for register: tx payload reg53 */
/* definitions for register: tx payload reg54 */
/* definitions for register: tx payload reg55 */
/* definitions for register: tx payload reg56 */
/* definitions for register: tx payload reg57 */
/* definitions for register: tx payload reg58 */
/* definitions for register: tx payload reg59 */
/* definitions for register: tx payload reg60 */
/* definitions for register: tx payload reg61 */
/* definitions for register: tx payload reg62 */
/* definitions for register: tx payload reg63 */
/* definitions for register: tx payload reg64 */
/* definitions for register: tx payload reg65 */
/* definitions for register: tx payload reg66 */
/* definitions for register: tx payload reg67 */
/* [0x0]: REG Version register */
#define MASTERFIP_REG_VER 0x00000000
/* [0x4]: REG rst */
#define MASTERFIP_REG_RST 0x00000004
/* [0x8]: REG core id */
#define MASTERFIP_REG_ID 0x00000008
/* [0xc]: REG leds and debug */
#define MASTERFIP_REG_LED 0x0000000c
/* [0x10]: REG fmc temperature */
#define MASTERFIP_REG_DS1820_TEMPER 0x00000010
/* [0x14]: REG fmc unique id lsb */
#define MASTERFIP_REG_DS1820_ID_LSB 0x00000014
/* [0x18]: REG fmc unique id msb */
#define MASTERFIP_REG_DS1820_ID_MSB 0x00000018
/* [0x1c]: REG ext sync ctrl */
#define MASTERFIP_REG_EXT_SYNC_CTRL 0x0000001c
/* [0x20]: REG ext sync pulses cnt */
#define MASTERFIP_REG_EXT_SYNC_P_CNT 0x00000020
/* [0x24]: REG bus speed */
#define MASTERFIP_REG_SPEED 0x00000024
/* [0x28]: REG macrocycle lgth */
#define MASTERFIP_REG_MACROCYC 0x00000028
/* [0x2c]: REG macrocycle time cnt */
#define MASTERFIP_REG_MACROCYC_TIME_CNT 0x0000002c
/* [0x30]: REG macrocycles number cnt */
#define MASTERFIP_REG_MACROCYC_NUM_CNT 0x00000030
/* [0x34]: REG turnaround lgth */
#define MASTERFIP_REG_TURNAR 0x00000034
/* [0x38]: REG turnaround time cnt */
#define MASTERFIP_REG_TURNAR_TIME_CNT 0x00000038
/* [0x3c]: REG silence lgth */
#define MASTERFIP_REG_SILEN 0x0000003c
/* [0x40]: REG silence time cnt */
#define MASTERFIP_REG_SILEN_TIME_CNT 0x00000040
/* [0x44]: REG tx ctrl */
#define MASTERFIP_REG_TX_CTRL 0x00000044
/* [0x48]: REG tx status */
#define MASTERFIP_REG_TX_STAT 0x00000048
/* [0x4c]: REG FielDrive wdgn, cdn */
#define MASTERFIP_REG_FD 0x0000004c
/* [0x50]: REG FielDrive wdg timestamp */
#define MASTERFIP_REG_FD_WDG_TSTAMP 0x00000050
/* [0x54]: REG FielDrive txer cnt */
#define MASTERFIP_REG_FD_TXER_CNT 0x00000054
/* [0x58]: REG FielDrive txer tstamp */
#define MASTERFIP_REG_FD_TXER_TSTAMP 0x00000058
/* [0x5c]: REG rx ctrl */
#define MASTERFIP_REG_RX_CTRL 0x0000005c
/* [0x60]: REG rx status */
#define MASTERFIP_REG_RX_STAT 0x00000060
/* [0x64]: REG rx current word index */
#define MASTERFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000064
/* [0x68]: REG rx num of frames with CRC error */
#define MASTERFIP_REG_RX_STAT_CRC_ERR_CNT 0x00000068
/* [0x6c]: REG rx payload ctrl byte */
#define MASTERFIP_REG_RX_PAYLD_CTRL 0x0000006c
/* [0x70]: REG rx payload reg1 */
#define MASTERFIP_REG_RX_PAYLD_REG1 0x00000070
/* [0x74]: REG rx payload reg2 */
#define MASTERFIP_REG_RX_PAYLD_REG2 0x00000074
/* [0x78]: REG rx payload reg3 */
#define MASTERFIP_REG_RX_PAYLD_REG3 0x00000078
/* [0x7c]: REG rx payload reg4 */
#define MASTERFIP_REG_RX_PAYLD_REG4 0x0000007c
/* [0x80]: REG rx payload reg5 */
#define MASTERFIP_REG_RX_PAYLD_REG5 0x00000080
/* [0x84]: REG rx payload reg6 */
#define MASTERFIP_REG_RX_PAYLD_REG6 0x00000084
/* [0x88]: REG rx payload reg7 */
#define MASTERFIP_REG_RX_PAYLD_REG7 0x00000088
/* [0x8c]: REG rx payload reg8 */
#define MASTERFIP_REG_RX_PAYLD_REG8 0x0000008c
/* [0x90]: REG rx payload reg9 */
#define MASTERFIP_REG_RX_PAYLD_REG9 0x00000090
/* [0x94]: REG rx payload reg10 */
#define MASTERFIP_REG_RX_PAYLD_REG10 0x00000094
/* [0x98]: REG rx payload reg11 */
#define MASTERFIP_REG_RX_PAYLD_REG11 0x00000098
/* [0x9c]: REG rx payload reg12 */
#define MASTERFIP_REG_RX_PAYLD_REG12 0x0000009c
/* [0xa0]: REG rx payload reg13 */
#define MASTERFIP_REG_RX_PAYLD_REG13 0x000000a0
/* [0xa4]: REG rx payload reg14 */
#define MASTERFIP_REG_RX_PAYLD_REG14 0x000000a4
/* [0xa8]: REG rx payload reg15 */
#define MASTERFIP_REG_RX_PAYLD_REG15 0x000000a8
/* [0xac]: REG rx payload reg16 */
#define MASTERFIP_REG_RX_PAYLD_REG16 0x000000ac
/* [0xb0]: REG rx payload reg17 */
#define MASTERFIP_REG_RX_PAYLD_REG17 0x000000b0
/* [0xb4]: REG rx payload reg18 */
#define MASTERFIP_REG_RX_PAYLD_REG18 0x000000b4
/* [0xb8]: REG rx payload reg19 */
#define MASTERFIP_REG_RX_PAYLD_REG19 0x000000b8
/* [0xbc]: REG rx payload reg20 */
#define MASTERFIP_REG_RX_PAYLD_REG20 0x000000bc
/* [0xc0]: REG rx payload reg21 */
#define MASTERFIP_REG_RX_PAYLD_REG21 0x000000c0
/* [0xc4]: REG rx payload reg22 */
#define MASTERFIP_REG_RX_PAYLD_REG22 0x000000c4
/* [0xc8]: REG rx payload reg23 */
#define MASTERFIP_REG_RX_PAYLD_REG23 0x000000c8
/* [0xcc]: REG rx payload reg24 */
#define MASTERFIP_REG_RX_PAYLD_REG24 0x000000cc
/* [0xd0]: REG rx payload reg25 */
#define MASTERFIP_REG_RX_PAYLD_REG25 0x000000d0
/* [0xd4]: REG rx payload reg26 */
#define MASTERFIP_REG_RX_PAYLD_REG26 0x000000d4
/* [0xd8]: REG rx payload reg27 */
#define MASTERFIP_REG_RX_PAYLD_REG27 0x000000d8
/* [0xdc]: REG rx payload reg28 */
#define MASTERFIP_REG_RX_PAYLD_REG28 0x000000dc
/* [0xe0]: REG rx payload reg29 */
#define MASTERFIP_REG_RX_PAYLD_REG29 0x000000e0
/* [0xe4]: REG rx payload reg30 */
#define MASTERFIP_REG_RX_PAYLD_REG30 0x000000e4
/* [0xe8]: REG rx payload reg31 */
#define MASTERFIP_REG_RX_PAYLD_REG31 0x000000e8
/* [0xec]: REG rx payload reg32 */
#define MASTERFIP_REG_RX_PAYLD_REG32 0x000000ec
/* [0xf0]: REG rx payload reg33 */
#define MASTERFIP_REG_RX_PAYLD_REG33 0x000000f0
/* [0xf4]: REG rx payload reg34 */
#define MASTERFIP_REG_RX_PAYLD_REG34 0x000000f4
/* [0xf8]: REG rx payload reg35 */
#define MASTERFIP_REG_RX_PAYLD_REG35 0x000000f8
/* [0xfc]: REG rx payload reg36 */
#define MASTERFIP_REG_RX_PAYLD_REG36 0x000000fc
/* [0x100]: REG rx payload reg37 */
#define MASTERFIP_REG_RX_PAYLD_REG37 0x00000100
/* [0x104]: REG rx payload reg38 */
#define MASTERFIP_REG_RX_PAYLD_REG38 0x00000104
/* [0x108]: REG rx payload reg39 */
#define MASTERFIP_REG_RX_PAYLD_REG39 0x00000108
/* [0x10c]: REG rx payload reg40 */
#define MASTERFIP_REG_RX_PAYLD_REG40 0x0000010c
/* [0x110]: REG rx payload reg41 */
#define MASTERFIP_REG_RX_PAYLD_REG41 0x00000110
/* [0x114]: REG rx payload reg42 */
#define MASTERFIP_REG_RX_PAYLD_REG42 0x00000114
/* [0x118]: REG rx payload reg43 */
#define MASTERFIP_REG_RX_PAYLD_REG43 0x00000118
/* [0x11c]: REG rx payload reg44 */
#define MASTERFIP_REG_RX_PAYLD_REG44 0x0000011c
/* [0x120]: REG rx payload reg45 */
#define MASTERFIP_REG_RX_PAYLD_REG45 0x00000120
/* [0x124]: REG rx payload reg46 */
#define MASTERFIP_REG_RX_PAYLD_REG46 0x00000124
/* [0x128]: REG rx payload reg47 */
#define MASTERFIP_REG_RX_PAYLD_REG47 0x00000128
/* [0x12c]: REG rx payload reg48 */
#define MASTERFIP_REG_RX_PAYLD_REG48 0x0000012c
/* [0x130]: REG rx payload reg49 */
#define MASTERFIP_REG_RX_PAYLD_REG49 0x00000130
/* [0x134]: REG rx payload reg50 */
#define MASTERFIP_REG_RX_PAYLD_REG50 0x00000134
/* [0x138]: REG rx payload reg51 */
#define MASTERFIP_REG_RX_PAYLD_REG51 0x00000138
/* [0x13c]: REG rx payload reg52 */
#define MASTERFIP_REG_RX_PAYLD_REG52 0x0000013c
/* [0x140]: REG rx payload reg53 */
#define MASTERFIP_REG_RX_PAYLD_REG53 0x00000140
/* [0x144]: REG rx payload reg54 */
#define MASTERFIP_REG_RX_PAYLD_REG54 0x00000144
/* [0x148]: REG rx payload reg55 */
#define MASTERFIP_REG_RX_PAYLD_REG55 0x00000148
/* [0x14c]: REG rx payload reg56 */
#define MASTERFIP_REG_RX_PAYLD_REG56 0x0000014c
/* [0x150]: REG rx payload reg57 */
#define MASTERFIP_REG_RX_PAYLD_REG57 0x00000150
/* [0x154]: REG rx payload reg58 */
#define MASTERFIP_REG_RX_PAYLD_REG58 0x00000154
/* [0x158]: REG rx payload reg59 */
#define MASTERFIP_REG_RX_PAYLD_REG59 0x00000158
/* [0x15c]: REG rx payload reg60 */
#define MASTERFIP_REG_RX_PAYLD_REG60 0x0000015c
/* [0x160]: REG rx payload reg61 */
#define MASTERFIP_REG_RX_PAYLD_REG61 0x00000160
/* [0x164]: REG rx payload reg62 */
#define MASTERFIP_REG_RX_PAYLD_REG62 0x00000164
/* [0x168]: REG rx payload reg63 */
#define MASTERFIP_REG_RX_PAYLD_REG63 0x00000168
/* [0x16c]: REG rx payload reg64 */
#define MASTERFIP_REG_RX_PAYLD_REG64 0x0000016c
/* [0x170]: REG rx payload reg65 */
#define MASTERFIP_REG_RX_PAYLD_REG65 0x00000170
/* [0x174]: REG rx payload reg66 */
#define MASTERFIP_REG_RX_PAYLD_REG66 0x00000174
/* [0x178]: REG rx payload reg67 */
#define MASTERFIP_REG_RX_PAYLD_REG67 0x00000178
/* [0x17c]: REG tx ctrl byte */
#define MASTERFIP_REG_TX_PAYLD_CTRL 0x0000017c
/* [0x180]: REG tx payload reg1 */
#define MASTERFIP_REG_TX_PAYLD_REG1 0x00000180
/* [0x184]: REG tx payload reg2 */
#define MASTERFIP_REG_TX_PAYLD_REG2 0x00000184
/* [0x188]: REG tx payload reg3 */
#define MASTERFIP_REG_TX_PAYLD_REG3 0x00000188
/* [0x18c]: REG tx payload reg4 */
#define MASTERFIP_REG_TX_PAYLD_REG4 0x0000018c
/* [0x190]: REG tx payload reg5 */
#define MASTERFIP_REG_TX_PAYLD_REG5 0x00000190
/* [0x194]: REG tx payload reg6 */
#define MASTERFIP_REG_TX_PAYLD_REG6 0x00000194
/* [0x198]: REG tx payload reg7 */
#define MASTERFIP_REG_TX_PAYLD_REG7 0x00000198
/* [0x19c]: REG tx payload reg8 */
#define MASTERFIP_REG_TX_PAYLD_REG8 0x0000019c
/* [0x1a0]: REG tx payload reg9 */
#define MASTERFIP_REG_TX_PAYLD_REG9 0x000001a0
/* [0x1a4]: REG tx payload reg10 */
#define MASTERFIP_REG_TX_PAYLD_REG10 0x000001a4
/* [0x1a8]: REG tx payload reg11 */
#define MASTERFIP_REG_TX_PAYLD_REG11 0x000001a8
/* [0x1ac]: REG tx payload reg12 */
#define MASTERFIP_REG_TX_PAYLD_REG12 0x000001ac
/* [0x1b0]: REG tx payload reg13 */
#define MASTERFIP_REG_TX_PAYLD_REG13 0x000001b0
/* [0x1b4]: REG tx payload reg14 */
#define MASTERFIP_REG_TX_PAYLD_REG14 0x000001b4
/* [0x1b8]: REG tx payload reg15 */
#define MASTERFIP_REG_TX_PAYLD_REG15 0x000001b8
/* [0x1bc]: REG tx payload reg16 */
#define MASTERFIP_REG_TX_PAYLD_REG16 0x000001bc
/* [0x1c0]: REG tx payload reg17 */
#define MASTERFIP_REG_TX_PAYLD_REG17 0x000001c0
/* [0x1c4]: REG tx payload reg18 */
#define MASTERFIP_REG_TX_PAYLD_REG18 0x000001c4
/* [0x1c8]: REG tx payload reg19 */
#define MASTERFIP_REG_TX_PAYLD_REG19 0x000001c8
/* [0x1cc]: REG tx payload reg20 */
#define MASTERFIP_REG_TX_PAYLD_REG20 0x000001cc
/* [0x1d0]: REG tx payload reg21 */
#define MASTERFIP_REG_TX_PAYLD_REG21 0x000001d0
/* [0x1d4]: REG tx payload reg22 */
#define MASTERFIP_REG_TX_PAYLD_REG22 0x000001d4
/* [0x1d8]: REG tx payload reg23 */
#define MASTERFIP_REG_TX_PAYLD_REG23 0x000001d8
/* [0x1dc]: REG tx payload reg24 */
#define MASTERFIP_REG_TX_PAYLD_REG24 0x000001dc
/* [0x1e0]: REG tx payload reg25 */
#define MASTERFIP_REG_TX_PAYLD_REG25 0x000001e0
/* [0x1e4]: REG tx payload reg26 */
#define MASTERFIP_REG_TX_PAYLD_REG26 0x000001e4
/* [0x1e8]: REG tx payload reg27 */
#define MASTERFIP_REG_TX_PAYLD_REG27 0x000001e8
/* [0x1ec]: REG tx payload reg28 */
#define MASTERFIP_REG_TX_PAYLD_REG28 0x000001ec
/* [0x1f0]: REG tx payload reg29 */
#define MASTERFIP_REG_TX_PAYLD_REG29 0x000001f0
/* [0x1f4]: REG tx payload reg30 */
#define MASTERFIP_REG_TX_PAYLD_REG30 0x000001f4
/* [0x1f8]: REG tx payload reg31 */
#define MASTERFIP_REG_TX_PAYLD_REG31 0x000001f8
/* [0x1fc]: REG tx payload reg32 */
#define MASTERFIP_REG_TX_PAYLD_REG32 0x000001fc
/* [0x200]: REG tx payload reg33 */
#define MASTERFIP_REG_TX_PAYLD_REG33 0x00000200
/* [0x204]: REG tx payload reg34 */
#define MASTERFIP_REG_TX_PAYLD_REG34 0x00000204
/* [0x208]: REG tx payload reg35 */
#define MASTERFIP_REG_TX_PAYLD_REG35 0x00000208
/* [0x20c]: REG tx payload reg36 */
#define MASTERFIP_REG_TX_PAYLD_REG36 0x0000020c
/* [0x210]: REG tx payload reg37 */
#define MASTERFIP_REG_TX_PAYLD_REG37 0x00000210
/* [0x214]: REG tx payload reg38 */
#define MASTERFIP_REG_TX_PAYLD_REG38 0x00000214
/* [0x218]: REG tx payload reg39 */
#define MASTERFIP_REG_TX_PAYLD_REG39 0x00000218
/* [0x21c]: REG tx payload reg40 */
#define MASTERFIP_REG_TX_PAYLD_REG40 0x0000021c
/* [0x220]: REG tx payload reg41 */
#define MASTERFIP_REG_TX_PAYLD_REG41 0x00000220
/* [0x224]: REG tx payload reg42 */
#define MASTERFIP_REG_TX_PAYLD_REG42 0x00000224
/* [0x228]: REG tx payload reg43 */
#define MASTERFIP_REG_TX_PAYLD_REG43 0x00000228
/* [0x22c]: REG tx payload reg44 */
#define MASTERFIP_REG_TX_PAYLD_REG44 0x0000022c
/* [0x230]: REG tx payload reg45 */
#define MASTERFIP_REG_TX_PAYLD_REG45 0x00000230
/* [0x234]: REG tx payload reg46 */
#define MASTERFIP_REG_TX_PAYLD_REG46 0x00000234
/* [0x238]: REG tx payload reg47 */
#define MASTERFIP_REG_TX_PAYLD_REG47 0x00000238
/* [0x23c]: REG tx payload reg48 */
#define MASTERFIP_REG_TX_PAYLD_REG48 0x0000023c
/* [0x240]: REG tx payload reg49 */
#define MASTERFIP_REG_TX_PAYLD_REG49 0x00000240
/* [0x244]: REG tx payload reg50 */
#define MASTERFIP_REG_TX_PAYLD_REG50 0x00000244
/* [0x248]: REG tx payload reg51 */
#define MASTERFIP_REG_TX_PAYLD_REG51 0x00000248
/* [0x24c]: REG tx payload reg52 */
#define MASTERFIP_REG_TX_PAYLD_REG52 0x0000024c
/* [0x250]: REG tx payload reg53 */
#define MASTERFIP_REG_TX_PAYLD_REG53 0x00000250
/* [0x254]: REG tx payload reg54 */
#define MASTERFIP_REG_TX_PAYLD_REG54 0x00000254
/* [0x258]: REG tx payload reg55 */
#define MASTERFIP_REG_TX_PAYLD_REG55 0x00000258
/* [0x25c]: REG tx payload reg56 */
#define MASTERFIP_REG_TX_PAYLD_REG56 0x0000025c
/* [0x260]: REG tx payload reg57 */
#define MASTERFIP_REG_TX_PAYLD_REG57 0x00000260
/* [0x264]: REG tx payload reg58 */
#define MASTERFIP_REG_TX_PAYLD_REG58 0x00000264
/* [0x268]: REG tx payload reg59 */
#define MASTERFIP_REG_TX_PAYLD_REG59 0x00000268
/* [0x26c]: REG tx payload reg60 */
#define MASTERFIP_REG_TX_PAYLD_REG60 0x0000026c
/* [0x270]: REG tx payload reg61 */
#define MASTERFIP_REG_TX_PAYLD_REG61 0x00000270
/* [0x274]: REG tx payload reg62 */
#define MASTERFIP_REG_TX_PAYLD_REG62 0x00000274
/* [0x278]: REG tx payload reg63 */
#define MASTERFIP_REG_TX_PAYLD_REG63 0x00000278
/* [0x27c]: REG tx payload reg64 */
#define MASTERFIP_REG_TX_PAYLD_REG64 0x0000027c
/* [0x280]: REG tx payload reg65 */
#define MASTERFIP_REG_TX_PAYLD_REG65 0x00000280
/* [0x284]: REG tx payload reg66 */
#define MASTERFIP_REG_TX_PAYLD_REG66 0x00000284
/* [0x288]: REG tx payload reg67 */
#define MASTERFIP_REG_TX_PAYLD_REG67 0x00000288
#endif
rtl/wbgen/masterfip_wbgen2_csr.html deleted 100644 → 0
View file @ 0c53da28
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.par
View file @ 2b615c20
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Fri Jun 30 16:05:56 2017
PCBE13457:: Fri Jul 14 21:09:18 2017
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -10,20 +10,6 @@ spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to
'2112@lxlicen01,2112@lxlicen02,2112@lxlicen03'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to ';1702@lxlicen08'.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -36,16 +22,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,657 out of 54,576 23%
Number used as Flip Flops: 12,655
Number of Slice Registers: 12,708 out of 54,576 23%
Number used as Flip Flops: 12,706
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,206 out of 27,288 55%
Number used as logic: 11,694 out of 27,288 42%
Number using O6 output only: 8,716
Number using O5 output only: 395
Number using O5 and O6: 2,583
Number of Slice LUTs: 14,840 out of 27,288 54%
Number used as logic: 11,637 out of 27,288 42%
Number using O6 output only: 8,659
Number using O5 output only: 393
Number using O5 and O6: 2,585
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
......@@ -54,18 +40,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 684
Number with same-slice register load: 654
Number with same-slice carry load: 30
Number used exclusively as route-thrus: 375
Number with same-slice register load: 346
Number with same-slice carry load: 29
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,123 out of 6,822 75%
Number of occupied Slices: 5,320 out of 6,822 77%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 18,118
Number with an unused Flip Flop: 7,613 out of 18,118 42%
Number with an unused LUT: 2,912 out of 18,118 16%
Number of fully used LUT-FF pairs: 7,593 out of 18,118 41%
Number of LUT Flip Flop pairs used: 18,556
Number with an unused Flip Flop: 7,655 out of 18,556 41%
Number with an unused LUT: 3,716 out of 18,556 20%
Number of fully used LUT-FF pairs: 7,185 out of 18,556 38%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -124,8 +110,8 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
Starting initial Timing Analysis. REAL time: 19 secs
Finished initial Timing Analysis. REAL time: 20 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -136,13 +122,9 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
......@@ -150,334 +132,131 @@ WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_w
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 105195 unrouted; REAL time: 20 secs
Phase 1 : 105528 unrouted; REAL time: 21 secs
Phase 2 : 95925 unrouted; REAL time: 23 secs
Phase 2 : 96119 unrouted; REAL time: 24 secs
Phase 3 : 43159 unrouted; REAL time: 58 secs
Phase 3 : 49322 unrouted; REAL time: 1 mins 9 secs
Phase 4 : 44608 unrouted; (Setup:1033, Hold:9197, Component Switching Limit:0) REAL time: 1 mins 14 secs
Phase 4 : 51674 unrouted; (Setup:64, Hold:8333, Component Switching Limit:0) REAL time: 1 mins 30 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:967, Hold:8926, Component Switching Limit:0) REAL time: 4 mins 45 secs
Phase 6 : 0 unrouted; (Setup:967, Hold:8926, Component Switching Limit:0) REAL time: 4 mins 49 secs
Phase 7 : 0 unrouted; (Setup:597, Hold:8926, Component Switching Limit:0) REAL time: 10 mins 38 secs
Phase 8 : 0 unrouted; (Setup:597, Hold:8926, Component Switching Limit:0) REAL time: 10 mins 38 secs
Phase 9 : 0 unrouted; (Setup:597, Hold:8926, Component Switching Limit:0) REAL time: 10 mins 38 secs
Phase 10 : 0 unrouted; (Setup:597, Hold:0, Component Switching Limit:0) REAL time: 10 mins 39 secs
Phase 11 : 0 unrouted; (Setup:464, Hold:0, Component Switching Limit:0) REAL time: 10 mins 45 secs
Total REAL time to Router completion: 10 mins 45 secs
Total CPU time to Router completion: 11 mins 8 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4071 | 0.547 | 1.758 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 216 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/io_clk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 464 (Setup: 464, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 7
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | -0.203ns| 10.203ns| 5| 464
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.297ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.084ns| 4.916ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.242ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
buf_P_clk PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
24_Core_cmp_clk_in_buf_P_clk = PERIOD | | | | |
TIMEGRP "cmp_mock_turtle_gen | | | | |
_with_gennum_U_GN4124_Core_cmp_clk_in_buf | | | | |
_P_clk" TS_U_Node_Template_U_GN41 | | | | |
24_Core_cmp_clk_in_P_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_Node_Template_U_GN4124_Core_cmp_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
in_P_clk = PERIOD TIMEGRP "U_Node | | | | |
_Template/gen_with_gennum.U_GN4124_Core/c | | | | |
mp_clk_in/P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys = PERIO | MINPERIOD | 6.876ns| 3.124ns| 0| 0
D TIMEGRP "cmp_mock_turtle_pllout | | | | |
_clk_sys" TS_clk_125m_pllref_p_i / 0.8 HI | | | | |
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | N/A | N/A| N/A| N/A| N/A
24_Core_cmp_clk_in_feedback = PERIOD | | | | |
TIMEGRP "cmp_mock_turtle/gen_ | | | | |
with_gennum.U_GN4124_Core/cmp_clk_in/feed | | | | |
back" 20 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | N/A | N/A| N/A| N/A| N/A
24_Core_cmp_clk_in_rx_pllout_xs_int = | | | | |
PERIOD TIMEGRP "cmp_mock_tur | | | | |
tle_gen_with_gennum_U_GN4124_Core_cmp_clk | | | | |
_in_rx_pllout_xs_int" TS_cmp_mock | | | | |
_turtle_gen_with_gennum_U_GN4124_Core_cmp | | | | |
_clk_in_buf_P_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_125m_pllref_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_p_i | 8.000ns| 3.334ns| 2.499ns| 0| 0| 0| 0|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| sys | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk_125m_pllref_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 8.162ns| 0| 5| 0| 4840691|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 10.203ns| N/A| 5| 0| 4840691| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.916ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.916ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.916ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 10 mins 51 secs
Total CPU time to PAR completion: 11 mins 14 secs
Peak Memory Usage: 926 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 5 errors found.
Number of error messages: 0
Number of warning messages: 74
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
PAR done!
Phase 5 : 0 unrouted; (Setup:27343, Hold:8154, Component Switching Limit:0) REAL time: 17 mins 51 secs
syn/spec/spec_masterfip_mt.syr
View file @ 2b615c20
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syn/spec/spec_masterfip_mt_map.mrp
View file @ 2b615c20
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