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MasterFIP - Gateware
Commit 2089b59c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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updated submodules

parent 5226e9ce
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Showing with 536 additions and 478 deletions
wr-node-core @ 7e8e9c3f
Subproject commit 43f540e3dc9a75819cac1fcfe21f2354e88966a7
Subproject commit 7e8e9c3f584e283ac5ac321e4730c35d5038ee82
rtl/Manifest.py
View file @ 2089b59c
......@@ -6,8 +6,6 @@ files=[ "carrier_info.vhd",
"fmc_masterFIP_mezz.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"irq_generator.vhd",
"leds_manager.vhd",
"masterFIP_pkg.vhd",
"masterfip_rx.vhd",
"masterfip_tx.vhd",
......
rtl/fmc_masterFIP_core.vhd
View file @ 2089b59c
......@@ -196,7 +196,8 @@ begin
mf_config_host_speed_o => speed_host,
mf_config_host_ext_sync_term_en_n_o => open,
mf_config_host_subs_o => open,
mf_config_fmc_speed_i => speed_b1_i & speed_b0_i,
mf_config_fmc_speed_i(1) => speed_b1_i,
mf_config_fmc_speed_i(0) => speed_b0_i,
mf_config_fmc_speed_ok_i => speed_ok,
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
......@@ -524,4 +525,4 @@ fd_txena_o <= fd_txena;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 2089b59c
......@@ -9,8 +9,8 @@ peripheral {
-- reset --
-------------------------------------------------------------------------------
reg {
name = "rst";
prefix = "rst";
name = "Reset Register";
prefix = "RST";
description = "software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register.";
field {
......@@ -49,9 +49,9 @@ peripheral {
-- identification --
-------------------------------------------------------------------------------
reg {
name = "id";
name = "Identification Register";
description = "an identification value";
prefix = "id";
prefix = "ID";
field {
name = "an id value";
......@@ -68,7 +68,7 @@ peripheral {
-------------------------------------------------------------------------------
reg {
name = "config from host";
prefix = "config_host";
prefix = "CONFIG_HOST";
field {
name = "speed";
......@@ -109,7 +109,7 @@ peripheral {
-------------------------------------------------------------------------------
reg {
name = "config from fmc";
prefix = "config_fmc";
prefix = "CONFIG_FMC";
field {
name = "speed";
......@@ -139,8 +139,8 @@ peripheral {
-- timing --
-------------------------------------------------------------------------------
reg {
name = "macrocycle lgth";
prefix = "macrocyc";
name = "Macrocycle Length Register";
prefix = "MACROCYC";
field {
name = "macrocycle lgth";
......@@ -162,7 +162,7 @@ peripheral {
};
reg {
name = "turnaround lgth";
name = "Turnaround Length Register";
prefix = "turnar";
field {
......@@ -185,7 +185,7 @@ peripheral {
};
reg {
name = "silence lgth";
name = "Silence Length Register";
prefix = "silen";
field {
......@@ -209,7 +209,7 @@ peripheral {
reg {
name = "macrocycle time cnt";
name = "Macrocycle Time Counter";
prefix = "macrocyc_time_cnt";
field {
......@@ -224,7 +224,7 @@ peripheral {
reg {
name = "turnaround time cnt";
name = "Turnaround Time Counter";
prefix = "turnar_time_cnt";
field {
......@@ -238,7 +238,7 @@ peripheral {
};
reg {
name = "silence time cnt";
name = "Silence Time Counter";
prefix = "silen_time_cnt";
field {
......@@ -252,7 +252,7 @@ peripheral {
};
reg {
name = "ext sync tstamp";
name = "External Sync Timestamp";
prefix = "ext_sync_tstamp";
field {
......@@ -269,8 +269,8 @@ peripheral {
-- serializer ctrl --
-------------------------------------------------------------------------------
reg {
name = "tx ctrl";
prefix = "tx";
name = "TC Control Register";
prefix = "TX_CTRL";
field {
name = "tx rst";
......@@ -308,8 +308,8 @@ peripheral {
-- serializer stat --
-------------------------------------------------------------------------------
reg {
name = "tx status";
prefix = "tx";
name = "TX Status Register";
prefix = "TX_STATUS";
field {
name = "tx stopped";
......@@ -326,8 +326,8 @@ peripheral {
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
name = "FielDrive Status Register";
prefix = "FD_STATUS";
field {
name = "fd watchdog";
......@@ -351,8 +351,8 @@ peripheral {
-- deserializer ctrl --
-------------------------------------------------------------------------------
reg {
name = "rx ctrl";
prefix = "rx";
name = "RX Control";
prefix = "RX_CTRL";
description = "active high reset of the deserializer";
field {
......@@ -371,8 +371,8 @@ peripheral {
-- deserializer stat --
-------------------------------------------------------------------------------
reg {
name = "rx status";
prefix = "rx";
name = "RX Status";
prefix = "RX_STATUS";
field {
name = "rx preamble detected";
......@@ -428,8 +428,8 @@ peripheral {
-------------------------------------------------------------------------------
reg {
name = "rx ctrl byte";
prefix = "rx_data_ctrl";
name = "RX Control Byte";
prefix = "RX_DATA_CTRL";
description = "contains the 8-bits of the control field of a received frame";
field {
......@@ -920,7 +920,7 @@ peripheral {
-------------------------------------------------------------------------------
reg {
name = "tx ctrl byte";
name = "TX Control Byte";
prefix = "tx_data_ctrl";
description = "contains the 8-bits of the control field of a frame to transmit";
......
sw/common/rt/Makefile
View file @ 2089b59c
......@@ -31,6 +31,7 @@ $(OUTPUT): $(LDSCRIPT) $(OBJS)
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
$(SIZE) $(OUTPUT).elf
./genraminit $(OUTPUT).bin > $(OUTPUT).ram
clean:
rm -f $(OBJS) $(OUTPUT).bin
......
sw/fip_test/fip-test.c
View file @ 2089b59c
......@@ -10,16 +10,66 @@
#include <string.h>
#include <rt.h>
/**
* Well, the main :)
*/
int main()
#define FIP_BASE 0x10000
void rt_get_time(uint32_t *seconds, uint32_t *cycles)
{
*seconds = lr_readl(WRN_CPU_LR_REG_TAI_SEC);
*cycles = lr_readl(WRN_CPU_LR_REG_TAI_CYCLES);
}
/* magic constants below taken from Eva's Python test program */
void fip_reset()
{
dp_writel(0xCAFE0003, FIP_BASE + 0x00); // reset inactive
dp_writel(0xCAFE0000, FIP_BASE + 0x00); // reset active
dp_writel(0xCAFE0003, FIP_BASE + 0x00); // reset inactive
}
void fip_send_id_dat( uint32_t varid )
{
dp_writel(0x01, FIP_BASE + 0x2C); // rst tx
dp_writel(0x00, FIP_BASE + 0x2C); // release rst tx
dp_writel(0x3, FIP_BASE + 0xC4); // ctrl byte
dp_writel(varid, FIP_BASE + 0xC8); // varid 2 bytes
dp_writel(0x202, FIP_BASE + 0x2C); // tx start
}
int fip_rx()
{
int i;
for(;;)
int rx_status = dp_readl( FIP_BASE + 0x3c );
// Poll for a frame
if(rx_status & (1<<1) )
{
pp_printf("Hello!");
for(i=0;i<10000000;i++) asm volatile("nop");
int n_bytes = (rx_status >> 8) & 0x1ff;
uint32_t ctrl = dp_readl( FIP_BASE + 0x40 );
uint32_t b1 = dp_readl( FIP_BASE + 0x44 );
uint32_t b2 = dp_readl( FIP_BASE + 0x48 );
uint32_t b3 = dp_readl( FIP_BASE + 0x4c );
uint32_t b4 = dp_readl( FIP_BASE + 0x40 );
pp_printf("RX bytes %d ctrl %x data %x %x %x %x\n", n_bytes, ctrl, b1, b2, b3, b4);
dp_writel(0x01, FIP_BASE + 0x3C); // rst rx
dp_writel(0x00, FIP_BASE + 0x3C); // release rst rx
}
return 0;
}
main()
{
int i = 0;
fip_reset();
fip_send_id_dat(0x310);
for(;;)
{
i++;
}
}
\ No newline at end of file
syn/spec/spec_masterFIP.xise
View file @ 2089b59c
......@@ -9,871 +9,871 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="194"/>
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="196"/>
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="199"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_cons_bytes_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="200"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_cons_outcome.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="201"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_consumption.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="203"/>
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_engine_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="204"/>
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_fd_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="205"/>
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="208"/>
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="209"/>
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/>
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_production.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="212"/>
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="213"/>
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="214"/>
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_mezz.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="215"/>
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterFIP.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
</files>
......@@ -902,7 +902,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -1203,9 +1203,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/spec_masterFIP" xil_pn:name="../../top/spec/spec_masterFIP.ucf"/>
</bindings>
<bindings/>
<libraries/>
......
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @ 2089b59c
......@@ -93,6 +93,7 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -199,7 +200,7 @@
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -219,6 +220,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -228,7 +230,7 @@
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
......
top/spec_wrnode/spec_top.ucf
View file @ 2089b59c
......@@ -223,3 +223,6 @@ NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n" TIG;
NET "U_Node_Template/U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
top/spec_wrnode/spec_top.vhd
View file @ 2089b59c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-07-27
-- Last update: 2015-08-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -307,6 +307,11 @@ begin
-- Aux
aux_o => aux);
fmc_dp_wb_in.err <= '0';
fmc_dp_wb_in.rty <= '0';
fmc_dp_wb_in.int <= '0';
fd_txena_o <= fd_txena;
-- LEDs font panel
......
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