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MasterFIP - Gateware
Commit 0cea86ef authored by Evangelia Gousiou's avatar Evangelia Gousiou
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rtl/fmc_masterFIP_core.vhd
View file @ 0cea86ef
......@@ -39,7 +39,7 @@
-- |________________________________________________________________| |
-- Figure 1: fmc_masterFIP_core architecture |
-- |
-- MrFIP WBGEN2 CSR: |
-- MASTERFIP WBGEN2 CSR: |
-- The mrfip_wbgen2_csr module has been generated through the wbgen2 application. |
-- It establishes the interface with the processor, usually a Mock Turtle core. |
-- This interface contains a set of control and status registers for each one of the |
......@@ -65,7 +65,7 @@
-- - copies all the payload registers (tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67)|
-- and the register that indicates the number of payload bytes to |
-- serialize (tx_ctrl_bytes_num) |
-- - starts serializing a WorldFIP frame (see following figure). Note that the FSS, |
-- - starts serializing a WorldFIP frame (see following Figure). Note that the FSS, |
-- CRC and FES fields are generated internally in the masterfip_tx unit. |
-- - after the FES, rises the tx_stat_stop status bit to signal the MT for the end |
-- of a successful frame transmission. |
......@@ -102,26 +102,26 @@
-- |
-- <---2 bytes--><-1byte-><------ rx_ctrl_bytes_num -------><--2 bytes--><-1byte-> |
-- |
-- Figure 2: WorldFIP rx frame structure |
-- Figure 3: WorldFIP rx frame structure |
-- |
-- EXT SYNC PULSE: |
-- The modules regarding the ext_sync_pulse are synchronising, deglitching and |
-- counting the number of rising-edge pulses that are arriving to the ext_sync input |
-- of the board and provide the result to the dedicated masterfip_wbgen2_csr register|
-- of the board and provide the result to a dedicated masterfip_wbgen2_csr register. |
-- |
-- MACROCYCLE: |
-- The modules regarding the macrocycle are counting the time of a macrocycle using |
-- the 10 ns input clock as well as the number of macrocycles since startup/a reset. |
-- Dedicated registers in the masterfip_wbgen2_csr provide the counters values |
-- to the processor (MT). Note that the macrocycle length comes from the processor |
-- through a dedicated register in the masterfip_wbgen2_csr and should be set once |
-- in the application startup. |
-- through another dedicated register in the masterfip_wbgen2_csr and should be set |
-- once in the application startup. |
-- |
-- TURNAROUND, SILENCE TIMES: |
-- The modules regarding the turnaround and silence time are counting the respective |
-- time using the 10 ns clock. Dedicated regs in the masterfip_wbgen2_csr provide |
-- the counters values to the processor (MT). As in the case of the macrocycle length|
-- the turnaround and silence time length is provided through dedicated registers in |
-- the turnaround and silence time length is provided through other dedicated regs in|
-- the masterfip_wbgen2_csr that should be set once in the application startup. |
-- |
-- ONEWIRE: |
......
rtl/masterFIP_pkg.vhd
View file @ 0cea86ef
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -12,14 +12,13 @@
---------------------------------------------------------------------------------------------------
-- File masterFIP_pkg.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- |
---------------- |
-- Last changes |
-- 09/2015 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -43,13 +42,12 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wf_package.all;
use work.masterfip_wbgen2_pkg.all;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specific package
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
--use work.wishbone_pkg.all;
--use work.gencores_pkg.all;
--=================================================================================================
......@@ -59,82 +57,12 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Constants regarding the SDB Devices Definitions --
-- Interface with MT --
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Devices sdb description
constant c_ONEWIRE_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000007",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000602", -- "WB-Onewire.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-Onewire.Control ")));
constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPEC.CSR ")));
constant c_I2C_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000606", -- "WB-I2C.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_MASTERFIP_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000003FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
---------------------------------------------------------------------------------------------------
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
constant C_BYTE_WIDTH : integer := 8;
constant C_WORD_WIDTH : integer := 32;
constant C_BYTE_WIDTH : integer := 8;
constant C_WORD_WIDTH : integer := 32;
-- Declaration of a structure with 67 words of 32-bit each = 268 bytes which represent the max
-- length of a frame, including
......@@ -168,31 +96,18 @@ package masterFIP_pkg is
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
constant c_SUBS_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
constant c_FMC_ONEWIRE_NB : integer := 1;
-- constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constants regarding the Carrier CSR info --
---------------------------------------------------------------------------------------------------
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant c_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
......@@ -253,16 +168,6 @@ package masterFIP_pkg is
end component;
---------------------------------------------------------------------------------------------------
component spec_reset_gen is
port
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
----------------------------------------------------------------------------------------------------
component masterfip_rx is
port
......@@ -328,12 +233,10 @@ package masterFIP_pkg is
end component incr_counter;
end masterFIP_pkg;
--=================================================================================================
-- package end
--=================================================================================================
end masterFIP_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
rtl/masterfip_tx.vhd
View file @ 0cea86ef
......@@ -33,7 +33,7 @@
-- o TX OSC this unit comes unmodified from the nanoFIP project. |
-- It generates the output FD_TXCK as well as an array of pulses, |
-- tx_sched_p_buff, used for the synchronization of the |
-- TX SERIALIZER's actions. |
-- TX SERIALIZER's actions. |
-- |
-- o DATA RETRIEVAL this unit copies the bytes provided by the processor (MT) |
-- upon the activation of the signal tx_start. |
......
rtl/wf_package.vhd
View file @ 0cea86ef
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -12,9 +12,18 @@
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 02/2016 |
-- Description Definitions of constants, types, entities, functions related to WorldFIP |
-- serialization and deserialization; the package is essential for all the modules |
-- coming from the nanoFIP design. |
-- As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was |
-- needed to have a new wf_package. In principle the nanoFIP design could have been |
-- modified to accept generics rather than constants, however as it is a stable |
-- design it was decided to keep it as it is and use for synthesis this package |
-- rather than the one coming with the nanoFIP submodule. |
-- A different package, the masterfip_pkg is used in the masterfip design for all |
-- other topics, not related to the WorldFIP serialization/ deserialization. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -50,33 +59,34 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the user clock --
-- Constants regarding the system clock --
---------------------------------------------------------------------------------------------------
-- 10ns clock for the masterFIP_core; same for the CPUs
-- 10ns clock for the masterFIP_core; same for the CPUs
constant c_QUARTZ_PERIOD_NS : real := 10.0;
constant c_QUARTZ_FREQ_MHZ : real := 100.0;
constant c_QUARTZ_PERIOD_NS : real := 10.0;
constant c_QUARTZ_FREQ_MHZ : real := 100.0;
constant c_QUARTZ_FREQ_MHZ_INT : integer := 100;
constant c_1SEC_CNT_LGTH : natural := 27;
constant c_1SEC_CLK_TICKS : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
constant c_1SEC_CNT_LGTH : natural := 27; -- lgth of counter that counts 1 sec using the sys clk
constant c_1SEC_CLK_TICKS : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
c_1SEC_CNT_LGTH);
---------------------------------------------------------------------------------------------------
-- Constants regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- To add a robust layer of protection to the FSMs of the design, counters that depend only on
-- the system clock have being implemented; when they are filled up, they can bring the FSMs back
-- to the IDLE state.
-- To add a robust layer of protection to the FSMs of the design (WorldFIP serializer and
-- deserializer), counters that depend only on the system clock have being implemented; when they
-- are filled up, they can bring the FSMs back to the IDLE state.
-- For the wf_rx_deserializer/wf_tx_serializer at the slowest bit rate, 31.25 kbps, the
-- reception/transmission of the longest frame takes:
-- 268 bytes RP_DAT = 68608 us
-- reception/transmission of the longest frame takes: 268 bytes RP_DAT = 68608 us
-- This demands for a 23 bits counter.
-- This for example means that if after 83 ms the reception/transmission of a frame has not been
-- completed, the respective FSMs will be reset.
-- This means that if after 83 ms the reception/transmission of a frame has not been completed,
-- the respective FSMs will be reset.
constant c_SESSION_TIMEOUT_C_LGTH : natural := 23; -- 83 ms
......@@ -84,7 +94,6 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
constant c_DEGLITCH_THRESHOLD : natural := 10;
......@@ -99,7 +108,6 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant c_VP : std_logic_vector (1 downto 0) := "11";
constant c_VN : std_logic_vector (1 downto 0) := "00";
constant c_ONE : std_logic_vector (1 downto 0) := "10";
......@@ -114,14 +122,12 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the Transmitter --
---------------------------------------------------------------------------------------------------
constant c_TX_SCHED_BUFF_LGTH : natural := 4; -- length of the buffer of pulses used for
-- the transmission synchronization
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
......@@ -132,8 +138,7 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the bit rate --
---------------------------------------------------------------------------------------------------
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
-- Calculation of the number of clk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LGTH : natural := 12; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
......
top/spec/spec_masterfip_mt.vhd
View file @ 0cea86ef
......@@ -13,9 +13,74 @@
-- File spec_masterfip.vhd |
-- |
-- Description Top level of the masterFIP design on a SPEC carrier. |
-- Figure 1 shows the architecture of the unit......
-- There is only one clock domain in the whole design. It is the 100 MHz clock
-- generated within the spec_node_template from the 125 MHz SPEC PLL clk_125m_pllref.
-- Both MT CPUs as well as the fmc_masterfip are running with this clock.
--
-- Figure 1 shows the architecture of the unit; the main units are:
-- ______________________________________________________________________ |
-- | | |
-- | _______________________________________ | |
-- | | SPEC NODE TEMPLATE | | |
-- _ | | _____ | | |
-- | | | | ___ | | | | |
-- |F| | |--- |----------------------| | | | | | |
-- |I| | _____ | | | | | | | | |
-- |E| | | | | | |---------------| | | | | | |
-- |L| <--| | | | | | HMQs | | | | | | |
-- |D| | | F | | | | | | | | | | |
-- |R| | | M | | | __ |__ | | | | | | |
-- |I| -->| | C | | | | | | | | | | | |
-- |V| | | | |----|--| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ | | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | | | | SH. | | a | | 4 | | | host |
-- | | S |----|Xbar|--| | ______ | MEM | | r | | 1 | | | |
-- ext plse --> | | T | |____| | | | | |_____| | | | 2 | | | |
-- | | E | | | | CPU1 | | | | 4 | | | |
-- | | R | |----|--|______| | | | | | | |
-- FMC 1wire <-->| | F | | | | | | | | | |
-- | | I | | | HMQs | | | | | | |
-- | | P | | |----------------|___| | | | | |
-- FMC LEDs <--| | | | |_____| | | |
-- | |_____| | _^_ | | |
-- | | | | | | |
-- | | |VIC| | | |
-- | | |___| | | |
-- | |_______________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_mt architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
-- On one side it is the interface to the FMC hardware: FielDrive chip, external |
-- pulse LEMO, 1-wire DS18B20 chip, LEDs; on the other side is has a wbgen2 WISHBONE |
-- where a set of control and status registers have been defined to interface with |
-- where a set of control and status registers have been defined to interface with |
-- the spec_node_template. |
-- The core is ignorant of the notion of the WorldFIP frame type (ID_DAT/RT_DAT/etc),|
-- of the macrocycle sequence or macrocycle timing; the sw running on the CPUs in |
-- the spec_node_template is responsible for managing these issues and for providing |
-- to this core all the payload bytes (that have been retrieved from the host) that |
-- need to be serializedand and a serialization startup trigger, or for enabling the |
-- deserializer and then providing to the host the deserialized bytes. |
-- Figure 2 shows the structure of a WorldFIP frame. The core is internally |
-- generating (serialization) or validating (deserialization) only the FSS, CRC and |
-- FES bytes; the rest of the bytes are retrieved from or provided to the |
-- spec_node_template. The core also encodes/decodes all the bytes to/from the |
-- Manchester2 code (as specified by the WorldFIP protocol) and controls/monitors |
-- all the FielDrive signals. |
-- _____________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________Payload_____________|_____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP frame structure |
-- |
-- SPEC NODE TEMPLATE: |
-- Instead of implementing a big FSM in HDL that would have been executing the |
-- WorldFIP macrocycle, it was easier to put this complexity into software running in|
-- an embedded CPU. The spec_node_template is a generic core that offers multi-CPU
-- processing and all the infrastructure around.
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -33,19 +98,17 @@
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_1164.all; -- std_logic definitions
use IEEE.numeric_std.all; -- conversion functions
library work;
use work.wishbone_pkg.all;
use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.masterfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
use work.wishbone_pkg.all; -- for the wb_crossbar
use work.spec_node_pkg.all; -- for the spec_node_template definition
use work.wr_node_pkg.all; -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all; -- for the HMQ
use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_mt is
generic (g_simulation : boolean := false);
......@@ -152,61 +215,87 @@ architecture rtl of spec_masterfip_mt is
---------------------------------------------------------------------------------------------------
-- Mock Turtle CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
-- - 1: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed variables
-- (only for the case of identif variable, scheduled as periodic variable, by radMon app)
-- - 2: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed messages
-- - 3: HMQ from CPU0 with the WorldFIP payloads from periodic consumed diagnostic variables
-- (only for the case of the FIPdiag variable 0x067F)
-- - 4: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed diagnostic variables
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
-- 2 "in HMQs" from the host -> towards MT
-- - 0: HMQ towards CPU0 with commands for the bus config, used only at startup (e.g.: HW_RESET,
-- PROGRAM_BA, BA_START, BA_RUNNING)
-- - 1: HMQ towards CPU1 with the payloads for produced WorldFIP frames (variables and messages;
-- CPU1 then puts this data into the Shared Memory for CPU0 to access and put them in the bus)
-- as well as requests for report data, requests for the scheduling of aperiodic traffic
-- (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8,
out_slot_config =>
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP period cons vars
1 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiod cons vars
2 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiod msgs
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS period vars
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiod vars
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (var/msg programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command-response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command-response
others => (0, 0)),
in_slot_count => 2,
in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus config (commands like: PROGRAM_BA, HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (commands like: BA_STOP, SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
others => (0, 0))); -- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
(out_slot_count => 8, -- MT -> towards the host
out_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
2 => (width => 128, entries => 4),
3 => (width => 128, entries => 4),
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
6 => (width => 128, entries => 4),
7 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 2, -- host -> towards MT
in_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0), -- in bytes
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys, rst_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
-- LEDs
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
......@@ -291,8 +380,6 @@ begin
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
rst_sys <= not rst_n_sys;
---------------------------------------------------------------------------------------------------
......@@ -304,7 +391,7 @@ begin
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_xwb_crossbar : xwb_crossbar
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
g_num_slaves => 1,
......@@ -410,7 +497,12 @@ begin
led_green_o <= spec_led(7);
led_red_o <= not rst_n_sys;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
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